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ds031 (v1.1) december 6, 2000 www.xilinx.com 33 advance product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. summary of virtex ? -ii features industry first platform fpga solution ip-immersion ? architecture - densities from 40k to 10m system gates - 420 mhz internal clock speed (advance data) - 840+ mb/s i/o (advance data) selectram ? memory hierarchy - 3.5 mb of true dual-port ? ram in 18-kbit block selectram resources - up to 1.9 mb of distributed selectram resources - high-performance interfaces to external memory 400 mb/s ddr-sdram interface (advance data) 400 mb/s fcram interface (advance data) 333 mb/s qdr ? -sram interface (advance data) 600 mb/s sigma ram interface (advance data) arithmetic functions - dedicated 18-bit x 18-bit multiplier blocks - fast look-ahead carry logic chains flexible logic resources - up to 122,880 internal registers / latches with clock enable - up to 122,880 look-up tables (luts) or cascadable 16-bit shift registers - wide multiplexers and wide-input function support - horizontal cascade chain and sum-of-products support - internal 3-state bussing high-performance clock management circuitry - up to 12 dcm (digital clock manager) modules precise clock de-skew flexible frequency synthesis high-resolution phase shifting emi reduction - 16 global clock multiplexer buffers active interconnect ? technology - fourth generation segmented routing structure - predictable, fast routing delay, independent of fanout selecti/o-ultra ? technology - up to 1,108 user i/os - 19 single-ended standards and six differential standards - programmable sink current (2 ma to 24 ma) per i/o -xcite ? digital controlled impedance (dci) i/o: on-chip termination resistors for single-ended i/o standards - pci-x @ 133 mhz, pci @ 66 mhz and 33 mhz compliance - differential signaling 840 mb/s low-voltage differential signaling i/o (lvds) with current mode drivers bus lvds i/o lightning data transport (ldt) i/o with current driver buffers low-voltage positive emitter-coupled logic (lvpecl) i/o built-in ddr input and output registers - proprietary high-performance selectlink ? technology high-bandwidth data path double data rate (ddr) link web-based hdl generation methodology supported by xilinx foundation ? and alliance ? series development systems - integrated vhdl and verilog design flows - compilation of 10m system gates designs - internet team design (itd) tool sram-based in-system configuration -fast selectmap ? configuration - triple data encryption standard (des) security option (bitstream encryption) - ieee1532 support - partial reconfiguration - unlimited re-programmability - readback capability power-down mode 0.15 m 8-layer metal process with 0.12 m high- speed transistors 1.5 v (v ccint ) core power supply, dedicated 3.3 v v ccaux auxiliary and v cco i/o power supplies ieee 1149.1 compatible boundary-scan logic support flip-chip and wire-bond ball grid array (bga) packages in three standard fine pitches (0.80mm, 1.00mm, and 1.27mm) 100% factory tested 0 virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 00 advance product specification r
virtex-ii 1.5v field-programmable gate arrays 34 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r general description the virtex-ii family is a platform fpga developed for high performance from low-density to high-density designs that are based on ip cores and customized modules. the family delivers complete solutions for telecommunication, wire- less, networking, video, and dsp applications, including pci, lvds, and ddr interfaces. the leading-edge 0.15m / 0.12m cmos 8-layer metal process and the virtex-ii architecture are optimized for high speed with low power consumption. combining a wide vari- ety of flexible features and a large range of densities up to 10 million system gates, the virtex-ii family enhances pro- grammable logic design capabilities and is a powerful alter- native to mask-programmed gates arrays. as shown in table 1 , the virtex-ii family comprises 12 members, ranging from 40k to 10m system gates. packaging offerings include ball grid array (bga) packages with 0.80mm, 1.00mm, and 1.27mm pitches. in addition to tradi- tional wire-bond interconnects, flip-chip interconnect is used in some of the bga offerings. the use of flip-chip interconnect offers more i/os than is possible in wire-bond versions of the similar packages. flip-chip construction offers the combination of high pin count with high thermal capacity. table 2 shows the maximum number of user i/os available. the virtex-ii device/package combination table ( table 41 at the end of this section) details the maximum number of i/os for each device and package using wire-bond or flip-chip technology. table 1: virtex-ii field-programmable gate array family members device system gates clb (1 clb = 4 slices = max 128 bits) multiplier blocks selectram blocks dcms max i/o pads array row x col. slices maximum distributed ram kbits 18-kbit blocks max ram (kbits) xc2v40 40k 8 x 8 256 8 4 4 72 4 88 xc2v80 80k 16 x 8 512 16 8 8 144 4 120 xc2v250 250k 24 x 16 1,536 48 24 24 432 8 200 xc2v500 500k 32 x 24 3,072 96 32 32 576 8 264 xc2v1000 1m 40 x 32 5,120 160 40 40 720 8 432 xc2v1500 1.5m 48 x 40 7,680 240 48 48 864 8 528 xc2v2000 2m 56 x 48 10,752 336 56 56 1,008 8 624 xc2v3000 3m 64 x 56 14,336 448 96 96 1,728 12 720 xc2v4000 4m 80 x 72 23,040 720 120 120 2,160 12 912 xc2v6000 6m 96 x 88 33,792 1,056 144 144 2,592 12 1,104 xc2v8000 8m 112 x 104 46,592 1,456 168 168 3,024 12 1,108 xc2v10000 10m 128 x 120 61,440 1,920 192 192 3,456 12 1,108 table 2: maximum number of user i/o pads device wire-bond flip-chip xc2v40 88 xc2v80 120 xc2v250 200 xc2v500 264 xc2v1000 328 432 xc2v1500 392 528 xc2v2000 456 624 xc2v3000 516 720 xc2v4000 912 xc2v6000 1,104 xc2v8000 1,108 xc2v10000 1,108
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 35 advance product specification 1-800-255-7778 r architecture virtex-ii array overview virtex-ii devices are user-programmable gate arrays with various configurable elements. the virtex-ii architecture is optimized for high-density and high-performance logic designs. as shown in figure 1 , the programmable device is comprised of input/output blocks (iobs) and internal configurable logic blocks (clbs). programmable i/o blocks provide the interface between package pins and the internal configurable logic. most pop- ular and leading-edge i/o standards are supported by the programmable iobs. the internal configurable logic includes four major elements organized in a regular array. configurable logic blocks (clbs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. bufts (3-state buffers) associated with each clb element drive dedicated segmentable horizontal routing resources. block selectram memory modules provide large 18-kbit storage elements of true dual-port ram. multiplier blocks are 18-bit x 18-bit dedicated multipliers. dcm (digital clock manager) blocks provide self- calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, coarse and fine-grained clock phase shifting, and electromagnetic interference (emi) reduction. a new generation of programmable routing resources called active interconnect technology interconnects all of these elements. the general routing matrix (grm) is an array of routing switches. each programmable element is tied to a switch matrix, allowing multiple connections to the general routing matrix. the overall programmable intercon- nection is hierarchical and designed to support high-speed designs. all programmable elements, including the routing resources, are controlled by values stored in static memory cells. these values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements. virtex-ii features this section briefly describes virtex-ii features. input/output blocks (iobs) iobs are programmable and can be categorized as follows: input block with an optional single-data-rate or double- data-rate (ddr) register output block with an optional single-data-rate or ddr register, and an optional 3-state buffer, to be driven directly or through a single or ddr register bi-directional block (any combination of input and output configurations) these registers are either edge-triggered d-type flip-flops or level-sensitive latches. iobs support the following single-ended i/o standards: lvttl, lvcmos (3.3 v, 2.5 v, 1.8 v, and 1.5 v) pci-x at 133 mhz, pci (3.3 v at 33 mhz and 66 mhz) figure 1: virtex-ii architecture overview global clock mux dcm dcm iob clb programmable i/os block selectram multiplier configurable logic ds031_28_100900
virtex-ii 1.5v field-programmable gate arrays 36 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r gtl and gtlp hstl (class i, ii, iii, and iv) sstl (3.3 v and 2.5 v, class i and ii) agp-2x the digital controlled impedance (dci) i/o feature automat- ically provides on-chip termination for each i/o element. the iob elements also support the following differential sig- naling i/o standards: lvds blvds (bus lvds) ulvds ldt lvpecl two adjacent pads are used for each differential pair. two or four iob blocks connect to one switch matrix to access the routing resources. configurable logic blocks (clbs) clb resources include four slices and two 3-state buffers. each slice is equivalent and contains: two function generators (f & g) two storage elements arithmetic logic gates large multiplexers wide function capability fast carry look-ahead chain horizontal cascade chain (or gate) the function generators f & g are configurable as 4-input look-up tables (luts), as 16-bit shift registers, or as 16-bit distributed selectram memory. in addition, the two storage elements are either edge-trig- gered d-type flip-flops or level-sensitive latches. each clb has internal fast interconnect and connects to a switch matrix to access general routing resources. block selectram memory the block selectram memory resources are 18 kb of true dual-port ram, programmable from 16k x 1 bit to 512 x 36 bits, in various depth and width configurations. each port is totally synchronous and independent, offering three "read- during-write" modes. block selectram memory is cascad- able to implement large embedded storage blocks. sup- ported memory configurations for dual-port and single-port modes are shown in table 3 . a multiplier block is associated with each selectram mem- ory block. the multiplier block is a dedicated 18 x 18-bit multiplier and is optimized for operations based on the block selectram content on one port. the 18 x 18 multiplier can be used independently of the block selectram resource. read/multiply/accumulate operations and dsp filter struc- tures are extremely efficient. both the selectram memory and the multiplier resource are connected to four switch matrices to access the general routing resources. global clocking the dcm and global clock multiplexer buffers provide a complete solution for designing high-speed clocking schemes. up to 12 dcm blocks are available. to generate de-skewed internal or external clocks, each dcm can be used to elimi- nate clock distribution delay. the dcm also provides 90-, 180-, and 270-degree phase-shifted versions of its output clocks. fine-grained phase shifting offers high-resolution phase adjustments in increments of 1/256 of the clock period. very flexible frequency synthesis provides a clock output frequency equal to any m/d ratio of the input clock frequency, where 1 m 4096 and 1 d 4096. for the exact timing parameters, see "virtex-ii electrical character- istics" on page 76 . virtex-ii devices have 16 global clock mux buffers, with up to eight clock nets per quadrant. each global clock mux buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. each dcm block is able to drive up to four of the 16 global clock mux buffers. routing resources the iob, clb, block selectram, multiplier, and dcm ele- ments all use the same interconnect scheme and the same access to the global routing matrix. timing models are shared, greatly improving the predictability of the perfor- mance of high-speed designs. there are a total of 16 global clock lines, with eight available per quadrant. in addition, 24 vertical and horizontal long lines per row or column as well as massive secondary and local routing resources provide fast interconnect. virtex-ii buffered interconnects are relatively unaffected by net fanout and the interconnect layout is designed to minimize crosstalk. horizontal and vertical routing resources for each row or column include: 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions) table 3: dual-port and single-port configurations 16k x 1 bit 2k x 9 bits 8k x 2 bits 1k x 18 bits 4k x 4 bits 512 x 36 bits
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 37 advance product specification 1-800-255-7778 r boundary scan boundary scan instructions and associated data registers support a standard methodology for accessing and config- uring virtex-ii devices that complies with ieee standards 1149.1 - 1993 and 1532. a system mode and a test mode are implemented. in system mode, a virtex-ii device per- forms its intended mission even while executing non-test boundary-scan instructions. in test mode, boundary-scan test instructions control the i/o pins for testing purposes. the virtex-ii test access port (tap) supports bypass, preload, sample, idcode, and usercode non-test instructions. the extest, intest, and highz test instructions are also supported. configuration virtex-ii devices are configured by loading data into internal configuration memory, using the following five modes: slave-serial mode master-serial mode slave selectmap mode master selectmap mode boundary-scan mode (ieee 1532) a data encryption standard (des) decryptor is available on-chip to secure the bitstreams. one or two triple-des key sets can be used to optionally encrypt the configuration information. readback and integrated logic analyzer configuration data stored in virtex-ii configuration memory can be read back for verification. along with the configura- tion data, the contents of all flip-flops/latches, distributed selectram, and block selectram memory resources can be read back. this capability is useful for real-time debug- ging. the integrated logic analyzer (ila) core and software pro- vides a complete solution for accessing and verifying virtex-ii devices. power-down mode activated by the power-down input, this mode reduces sup- ply current and retains the virtex-ii device configuration. detailed description input/output blocks (iobs) virtex-ii i/o blocks (iobs) are provided in groups of two or four on the perimeter of each device. each iob can be used as input and/or output for single-ended i/os. two iobs can be used as a differential pair. a differential pair is always connected to the same switch matrix, as shown in figure 2 . iob blocks are designed for high performances i/os, sup- porting 19 single-ended standards, as well as differential signaling with lvds, ldt, bus lvds, and lvpecl. figure 2: virtex-ii input/output tile iob pad4 iob pad3 differential pair iob pad2 iob pad1 differential pair switch matrix ds031_30_101600
virtex-ii 1.5v field-programmable gate arrays 38 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r supported i/o standards virtex-ii iob blocks feature selecti/o inputs and outputs that support a wide variety of i/o signaling standards. in addition to the internal supply voltage (v ccint = 1.5v), out- put driver supply voltage ( v cco ) is dependent on the i/o standard (see table 4 ). an auxiliary supply voltage (v ccaux = 3.3 v) is required, regardless of the i/o stan- dard used. for exact supply voltage absolute maximum rat- ings, see "dc input and output levels" on page 78 . all of the user iobs have fixed-clamp diodes to v cco and to ground. the iobs are not compatible or compliant with 5 v i/o standards (not 5 v tolerant). table 6 lists supported i/o standards with digital controlled impedance. see "digital controlled impedance (dci)" on page 43 . table 4: supported single-ended i/o standards i/o standard output v cco input v cco input v ref board termination voltage (v tt ) lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 1.5 1.5 n/a n/a pci33_3 3.3 3.3 n/a n/a pci66_3 3.3 3.3 n/a n/a pci-x 3.3 3.3 n/a n/a gtl n/a n/a 0.8 1.2 gtlp n/a n/a 1.0 1.5 hstl_i 1.5 n/a 0.75 0.75 hstl_ii 1.5 n/a 0.75 0.75 hstl_iii 1.5 n/a 0.9 1.5 hstl_iv 1.5 n/a 0.9 1.5 sstl2_i 2.5 n/a 1.25 1.25 sstl2_ii 2.5 n/a 1.25 1.25 sstl3_i 3.3 n/a 1.5 1.5 sstl3_ii 3.3 n/a 1.5 1.5 agp-2x/agp 3.3 n/a 1.32 n/a table 5: supported differential signal i/o standards i/o standard output v cco input v cco input v ref output v od lvpecl_33 3.3 n/a n/a v cco ? 1.025 to v cco ? 1.64 ldt_25 2.5 n/a n/a 0.430 - 0.670 lvds_33 3.3 n/a n/a 0.250 - 0.400 lvds_25 2.5 n/a n/a 0.250 - 0.400 lvdsext_33 3.3 n/a n/a 0.330 - 0.700 lvdsext_25 2.5 n/a n/a 0.330 - 0.700 blvds_25 2.5 n/a n/a 0.250 - 0.450 ulvds_25 2.5 n/a n/a 0.430 - 0.670 table 6: supported dci i/o standards i/o standard output v cco input v cco input v ref termination type lvdci_33 3.3 3.3 n/a series lvdci_dv2_33 3.3 3.3 n/a series lvdci_25 2.5 2.5 n/a series lvdci_dv2_25 2.5 2.5 n/a series lvdci_18 1.8 1.8 n/a series lvdci_dv2_18 1.8 1.8 n/a series lvdci_15 1.5 1.5 n/a series lvdci_dv2_15 1.5 1.5 n/a series gtl_dci 1.2 1.2 0.8 single gtlp_dci 1.5 1.5 1.0 single hstl_i_dci 1.5 1.5 0.75 split hstl_ii_dci 1.5 1.5 0.75 split hstl_iii_dci 1.5 1.5 0.9 single hstl_iv_dci 1.5 1.5 0.9 single sstl2_i_dci 2 2.5 2.5 1.25 split sstl2_ii_dci 2 2.5 2.5 1.25 split sstl3_i_dci 2 3.3 3.3 1.5 split sstl3_ii_dci 2 3.3 3.3 1.5 split notes: 1. lvdci_xx and lvdci_dv2_xx are lvcmos controlled impedance buffers, matching the reference resistors or half of the reference resistors. 2. these are sstl compatible.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 39 advance product specification 1-800-255-7778 r logic resources iob blocks include six storage elements, as shown in figure 3 . each storage element can be configured either as an edge- triggered d-type flip-flop or as a level-sensitive latch. on the input, output, and 3-state path, one or two ddr registers can be used. double data rate is directly accomplished by the two regis- ters on each path, clocked by the rising edges (or falling edges) from two different clock nets. the two clock signals are generated by the dcm and must be 180 degrees out of phase, as shown in figure 4 . there are two input, output, and 3-state data signals, each being alternately clocked out. figure 3: virtex-ii iob block reg ock1 reg ock2 reg ick1 reg ick2 ddr mux input pa d 3-state reg ock1 reg ock2 ddr mux output iob ds031_29_100900 figure 4: double data rate registers d1 clk1 ddr mux q1 fddr d2 clk2 (50/50 duty cycle clock) clock qq q2 d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 180 0 ds031_26_100900
virtex-ii 1.5v field-programmable gate arrays 40 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r this ddr mechanism can be used to mirror a copy of the clock on the output. this is useful for propagating a clock along the data that has an identical delay. it is also useful for multiple clock generation, where there is a unique clock driver for every clock load. virtex-ii devices can produce many copies of a clock with very little skew. each group of two registers has a clock enable signal (ice for the input registers, oce for the output registers, and tce for the 3-state registers). the clock enable signals are active high by default. if left unconnected, the clock enable for that storage element defaults to the active state. each iob block has common synchronous or asynchro- nous set and reset (sr and rev signals). sr forces the storage element into the state specified by the srhigh or srlow attribute. srhigh forces a logic ? 1 ? . srlow forces a logic ? 0 ? . when sr is used, a second input (rev) forces the storage element into the opposite state. the reset condition predominates over the set condition. the ini- tial state after configuration or global initialization state is defined by a separate init0 and init1 attribute. by default, the srlow attribute forces init0, and the srhigh attribute forces init1. for each storage element, the srhigh, srlow, init0, and init1 attributes are independent. synchronous or asynchronous set / reset is consistent in an iob block. all the control signals have independent polarity. any inverter placed on a control input is automatically absorbed. each register or latch (independent of all other registers or latches) (see figure 5 ) can be configured as follows: no set or reset synchronous set synchronous reset synchronous set and reset asynchronous set (preset) asynchronous reset (clear) asynchronous set and reset (preset and clear) the synchronous reset overrides a set, and an asynchro- nous clear overrides a preset. figure 5: register / latch configuration in an iob block ff latch sr rev d1 q1 ce ck1 ff latch sr rev d2 ff1 ff2 ddr mux q2 ce ck2 rev sr (o/t) clk1 (oq or tq) (o/t) ce (o/t) 1 (o/t) clk2 (o/t) 2 attribute init1 init0 srhigh srlow attribute init1 init0 srhigh srlow reset type sync async ds031_25_110300 shared by all registers
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 41 advance product specification 1-800-255-7778 r input/output individual options each device pad has optional pull-up, pull-down, and weak-keeper in lvttl and lvcmos selecti/o configurations, as illustrated in figure 6 . values of the optional pull-up and pull-down resistors are in the range 50 - 100 k w . the optional weak-keeper circuit is connected to each out- put. when selected, the circuit monitors the voltage on the pad and weakly drives the pin high or low. if the pin is con- nected to a multiple-source signal, the weak-keeper holds the signal in its last state if all drivers are disabled. maintain- ing a valid logic level in this way eliminates bus chatter; pull- up or pull-down override the weak-keeper circuit. lvttl sinks and sources current up to 24 ma. the current is programmable for lvttl and lvcmos selecti/o stan- dards (see table 7 ). drive-strength and slew-rate controls for each output driver, minimize bus transients. for lvdci and lvdci_dv2 standards, drive strength and slew-rate controls are not available. figure 6: lvttl, lvcmos or pci selecti/o standards v cco v cco v cco weak keeper program delay obuf ibuf program current clamp diode 50-100k ? 50-100k ? pa d v ccaux = 3.3v ds031_23_100900 v ccint = 1.5v table 7: lvttl and lvcmos programmable currents (sink and source) selecti/o programmable current (worst-case guaranteed minimum) lvttl 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma lvcmos33 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma lvcmos25 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma lvcmos18 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma n/a lvcmos15 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma n/a
virtex-ii 1.5v field-programmable gate arrays 42 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r figure 7 shows the sstl2, sstl3, and hstl configura- tions. hstl can sink current up to 48 ma. (hstl iv) all pads are protected against damage from electrostatic discharge (esd) and from over-voltage transients. virtex-ii uses two memory cells to control the configuration of an i/o as an input. this is to reduce the probability of an i/o con- figured as an input from flipping to an output when sub- jected to a single event upset (seu) in space applications. prior to configuration, all outputs not involved in configura- tion are forced into their high-impedance state. the pull- down resistors and the weak-keeper circuits are inactive. the dedicated pin hswap_en controls the pull-up resis- tors prior to configuration. by default, hswap_en is set high, which disables the pull-up resistors on user i/o pins. when hswap_en is set low, the pull-up resistors are acti- vated on user i/o pins. all virtex-ii iobs support ieee 1149.1 compatible boundary scan testing. input path the virtex-ii iob input path routes input signals directly to internal logic and / or through an optional input flip-flop or latch, or through the ddr input registers. an optional delay element at the d-input of the storage element eliminates pad-to-pad hold time. the delay is matched to the internal clock-distribution delay of the virtex-ii device, and when used, assures that the pad-to-pad hold time is zero. each input buffer can be configured to conform to any of the low-voltage signaling standards supported. in some of these standards the input buffer utilizes a user-supplied threshold voltage, v ref . the need to supply v ref imposes constraints on which standards can be used in the same bank. see i/o banking description. output path the output path includes a 3-state output buffer that drives the output signal onto the pad. the output and / or the 3-state signal can be routed to the buffer directly from the internal logic or through an output / 3-state flip-flop or latch, or through the ddr output / 3-state registers. each output driver can be individually programmed for a wide range of low-voltage signaling standards. in most sig- naling standards, the output high voltage depends on an externally supplied v cco voltage. the need to supply v cco imposes constraints on which standards can be used in the same bank. see i/o banking description. i/o banking some of the i/o standards described above require v cco and v ref voltages. these voltages are externally supplied and connected to device pins that serve groups of iob blocks, called banks. consequently, restrictions exist about which i/o standards can be combined within a given bank. eight i/o banks result from dividing each edge of the fpga into two banks, as shown in figure 8 and figure 9 . each bank has multiple v cco pins, all of which must be con- nected to the same voltage. this voltage is determined by the output standards in use. within a bank, output standards can be mixed only if they use the same v cco . compatible standards are shown in table 8 . gtl and gtlp appear under all voltages because their open-drain outputs do not depend on v cco . some input standards require a user-supplied threshold voltage, v ref . in this case, certain user-i/o pins are auto- matically configured as inputs for the v ref voltage. approx- imately one in six of the i/o pins in the bank assume this role. figure 7: sstl or hstl selecti/o standards v cco obuf v ref clamp diode pa d v ccaux = 3.3v v ccint = 1.5v ds031_24_100900 figure 8: virtex-ii i/o banks: top view for wire-bond packages (cs, fg, & bg) ug002_c2_014_112900 bank 0 bank 1 bank 5 bank 4 bank 7 bank 6 bank 2 bank 3
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 43 advance product specification 1-800-255-7778 r v ref pins within a bank are interconnected internally, and consequently only one v ref voltage can be used within each bank. however, for correct operation, all v ref pins in the bank must be connected to the external reference volt- age source. the v cco and the v ref pins for each bank appear in the device pinout tables. within a given package, the number of v ref and v cco pins can vary depending on the size of device. in larger devices, more i/o pins convert to v ref pins. since these are always a superset of the v ref pins used for smaller devices, it is possible to design a pcb that permits migration to a larger device if necessary. all v ref pins for the largest device anticipated must be con- nected to the v ref voltage and not used for i/o. in smaller devices, some v cco pins used in larger devices do not connect within the package. these unconnected pins can be left uncon- nected externally, or, if necessary, they can be connected to the v cco voltage to permit migration to a larger device. digital controlled impedance (dci) today ? s chip output signals with fast edge rates require ter- mination to prevent reflections and maintain signal integrity. high pin count packages (especially ball grid arrays) can not accommodate external termination resistors. virtex-ii dci provides controlled impedance drivers and on- chip termination for single-ended i/os. this eliminates the need for external resistors, and improves signal integrity. the dci feature can be used on any iob by selecting one of the dci i/o standards. when applied to inputs, dci provides input parallel termina- tion. when applied to outputs, dci provides controlled impedance drivers (series termination) or output parallel termination. dci operates independently on each i/o bank. when a dci i/o standard is used in a particular i/o bank, external refer- ence resistors must be connected to two dual-function pins on the bank. these resistors, voltage reference of n transis- tor (vrn) and the voltage reference of p transistor (vrp) are shown in figure 10 . when used with a terminated i/o standard, the value of the resistor is specified by the standard (typically 50 w ). when used with a controlled impedance driver, the resistor sets the output impedance of the driver within the specified range (25 w to 150 w) . the resistors connected to vrn and vrp do not need to be the same value. 1% resistors are recommended. the dci system adjusts the i/o impedance to match the two external reference resistors, or half of the reference resistor, and compensates for impedance changes due to voltage and/or temperature fluctuations. the adjustment is done by turning parallel transistors in the iob on or off. figure 9: virtex-ii i/o banks: top view for flip-chip packages (ff & bf) table 8: compatible output standards v cco compatible standards 3.3 v pci, lvttl, sstl3 (i & ii), agp-2x, lvds_33, lvdsext_33, lvcmos33, lvdci_33, lvdci_dv2_33, sstl3_dci (i & ii), blvds, lvpecl, gtl, gtlp 2.5 v sstl2 (i & ii), lvcmos25, gtl, gtlp, lvds_25, lvdsext_25, lvdci_25, lvdci_dv2_25, sstl2_dci (i & ii), ldt, ulvds, blvds 1.8 v lvcmos18, gtl, gtlp, lvdci_18, lvdci_dv2_18 1.5 v hstl (i, ii, iii, & iv), lvcmos15, gtl, gtlp, lvdci_15, lvdci_dv2_15, gtlp_dci, hstl_dci (i,ii, iii & iv) 1.2v gtl_dci ds031_66_112900 bank 1 bank 0 bank 4 bank 5 bank 2 bank 3 bank 7 bank 6 figure 10: dci in a virtex-ii bank ds031_50_101200 v cco gnd dci dci dci dci vrn vrp 1 bank r ref (1%) r ref (1%)
virtex-ii 1.5v field-programmable gate arrays 44 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r controlled impedance drivers (series termination) dci can be used to provide a buffer with a controlled output impedance. it is desirable for this output impedance to match the transmission line impedance (z). virtex-ii input buffers also support lvdci and lvdci_dv2 i/o standards. controlled impedance drivers (parallel termination) dci also provides on-chip termination for sstl3, sstl2, hstl (class i, ii, iii, or iv), and gtl/gtlp receivers or transmitters on bidirectional lines. table 10 lists the on-chip parallel terminations available in vir- tex-ii devices. v cco must be set according to table 6 . note that there is a v cco requirement for gtl_dci and gtlp_dci, due to the on-chip termination resistor. for further details, see the virtex-ii user manual. figure 11: internal series termination table 9: selecti/o controlled impedance buffers v cco dci dci half impedance 3.3 v lvdci_33 lvdci_dv2_33 2.5 v lvdci_25 lvdci_dv2_25 1.8 v lvdci_18 lvdci_dv2_18 1.5 v lvdci_15 lvdci_dv2_15 z iob z virtex-ii dci ds031_51_110600 v cco = 3.3 v, 2.5 v, 1.8 v or 1.5 v table 10: selecti/o buffers with on-chip parallel termination i/o standard external termination on-chip termination sstl3 class i sstl3_i sstl3_i_dci 1 sstl3 class ii sstl3_ii sstl3_ii_dci 1 sstl2 class i sstl2_i sstl2_i_dci 1 sstl2 class ii sstl2_ii sstl2_ii_dci 1 hstl class i hstl_i hstl_i_dci hstl class ii hstl_ii hstl_ii_dci hstl class iii hstl_iii hstl_iii_dci hstl class iv hstl_iv hstl_iv_dci gtl gtl gtl_dci gtlp gtlp gtlp_dci notes: 1. sstl compatible
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 45 advance product specification 1-800-255-7778 r figure 12 provides examples illustrating the use of the hstl_iv_dci, hstl_ii_dci, and sstl2_dci i/o standards. figure 12: dci usage examples z 0 rr hstl_iv_dci transmitter virtex-ii dci hstl_iv_dci receiver hstl_iv_dci transmitter and receiver v cco v cco z 0 rr v cco virtex-ii dci r v cco v cco hstl_iv z 0 r v cco r v cco virtex-ii dci z 0 r v cco virtex-ii dci z 0 rr hstl_ii_dci transmitter hstl_ii_dci receiver v cco /2 v cco /2 z 0 2r virtex-ii dci virtex-ii dci virtex-ii dci 2r r 2r v cco v cco /2 hstl_ii z 0 r v cco /2 2r v cco hstl_ii_dci transmitter and receiver sstl2_i_dci transmitter sstl2_i_dci receiver z 0 z 0 virtex-ii dci z 0 r v cco /2 r v cco /2 sstl2_i sstl2_i_dci transmitter and receiver 2r virtex-ii dci 2r v cco virtex-ii dci 2r z 0 2r v cco virtex-ii dci 2r 2r v cco z 0 virtex-ii dci 2r 2r v cco ds031_65_110200
virtex-ii 1.5v field-programmable gate arrays 46 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r configurable logic blocks (clbs) the virtex-ii configurable logic blocks (clb) are organized in an array and are used to build combinatorial and synchro- nous logic designs. each clb element is tied to a switch matrix to access the general routing matrix, as shown in figure 13 . a clb element comprises 4 similar slices, with fast local feedback within the clb. the four slices are split in two columns of two slices with two independent carry logic chains and one common shift chain. slice description introduction each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. as shown in figure 14 , each 4-input function generator is programmable as a 4-input lut, 16 bits of distributed selectram memory, or a 16-bit variable- tap shift register element. figure 13: virtex-ii clb element slice x1y1 slice x1y0 slice x0y1 slice x0y0 fast connects to neighbors switch matrix ds031_32_101600 shift cin cout tbuf x0y1 cout cin tbuf x0y0 figure 14: virtex-ii slice configuration register muxf5 muxfx cy srl16 ram16 lut g register arithmetic logic cy lut f ds031_31_100900 srl16 ram16 orcy
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 47 advance product specification 1-800-255-7778 r the output from the function generator in each slice drives both the slice output and the d input of the storage element. figure 15 shows a more detailed view of a single slice. configurations look-up table virtex-ii function generators are implemented as 4-input look-up tables (luts). four independent inputs are pro- vided to each of the two function generators in a slice (f and g). these function generators are each capable of imple- menting any arbitrarily defined boolean function of four inputs. the propagation delay is therefore independent of the function implemented. signals from the function gener- ators can exit the slice (x or y output), can input the xor dedicated gate (see arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the d input of the storage element, or go to the muxf5 (not shown in figure 15 ). in addition to the basic luts, the virtex-ii slice contains logic (muxf5 and muxfx multiplexers) that combines function generators to provide any function of five, six, seven, or eight inputs. the muxfx are either muxf6, muxf7 or muxf8 according to the slice considered in the clb. selected functions up to nine inputs (muxf5 multi- plexer) can be implemented in one slice. the muxfx can also be a muxf6, muxf7, or muxf8 multiplexers to map any functions of six, seven, or eight inputs and selected wide logic functions. figure 15: virtex-ii slice (top half) g4 sopin a4 g3 a3 g2 a2 g1 a1 wg4 wg4 wg3 wg3 wg2 wg2 wg1 by wg1 dual-port lut ff latch ram rom shift-reg d 0 mc15 ws sr sr rev di g y g2 g1 by 1 0 prod dq ce ce ck clk muxcy yb dig dy y o i muxcy o i i sopout dymux gymux ybmux orcy wsg we[2:0] shiftout cyog xorg we clk wsf altdig ce sr clk slicewe[2:0] multand shared between x & y registers shiftin cout cin ds031_01_110600 q
virtex-ii 1.5v field-programmable gate arrays 48 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r register/latch the storage elements in a virtex-ii slice can be configured either as edge-triggered d-type flip-flops or as level-sensi- tive latches. the d input can be directly driven by the x or y output via the dx or dy input, or by the slice inputs bypass- ing the function generators via the bx or by input. the clock enable signal (ce) is active high by default. if left unconnected, the clock enable for that storage element defaults to the active state. in addition to clock (ck) and clock enable (ce) signals, each slice has set and reset signals (sr and by slice inputs). sr forces the storage element into the state speci- fied by the attribute srhigh or srlow. srhigh forces a logic ? 1 ? when sr is asserted. srlow forces a logic ? 0 ? . when sr is used, a second input (by) forces the storage element into the opposite state. the reset condition is pre- dominant over the set condition. (see figure 16 .) the initial state after configuration or global initial state is defined by a separate init0 and init1 attribute. by default, setting the srlow attribute sets init0, and setting the srhigh attribute sets init1. for each slice, set and reset can be set to be synchronous or asynchronous. virtex-ii devices also have the ability to set init0 and init1 independent of srhigh and srlow. the control signals clock (clk), clock enable (ce) and set/reset (sr) are common to both storage elements in one slice. all of the control signals have independent polarity. any inverter placed on a control input is automatically absorbed. the set and reset functionality of a register or a latch can be configured as follows: no set or reset synchronous set synchronous reset synchronous set and reset asynchronous set (preset) asynchronous reset (clear) asynchronous set and reset (preset and clear) the synchronous reset has precedence over a set, and an asynchronous clear has precedence over a preset. distributed selectram memory each function generator (lut) can implement a 16 x 1-bit synchronous ram resource called a distributed selectram element. the selectram elements are configurable within a clb to implement the following: single-port 16 x 8 bit ram single-port 32 x 4 bit ram single-port 64 x 2 bit ram single-port 128 x 1 bit ram dual-port 16 x 4 bit ram dual-port 32 x 2 bit ram dual-port 64 x 1 bit ram distributed selectram memory modules are synchronous (write) resources. the combinatorial read access time is extremely fast, while the synchronous write simplifies high- speed designs. a synchronous read can be implemented with a storage element in the same slice. the distributed selectram memory and the storage element share the same clock input. a write enable (we) input is active high, and is driven by the sr input. table 11 shows the number of luts (2 per slice) occupied by each distributed selectram configuration. figure 16: register / latch configuration in a slice ff ffy latch sr rev dq ce ck yq ff ffx latch sr rev d q ce ck xq ce dx dy by clk bx sr attribute init1 init0 srhigh srlow attribute init1 init0 srhigh srlow reset type sync async ds031_22_110600 table 11: distributed selectram configurations ram number of luts 16 x 1s 1 16 x 1d 2 32 x 1s 2 32 x 1d 4 64 x 1s 4 64 x 1d 8 128 x 1s 8 notes: 1. s = single-port configuration; d = dual-port configuration
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 49 advance product specification 1-800-255-7778 r for single-port configurations, distributed selectram mem- ory has one address port for synchronous writes and asyn- chronous reads. for dual-port configurations, distributed selectram mem- ory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads. the func- tion generator (lut) has separated read address inputs (a1, a2, a3, a4) and write address inputs (wg1/wf1, wg2/wf2, wg3/wf3, wg4/wf4). in single-port mode, read and write addresses share the same address bus. in dual-port mode, one function genera- tor (r/w port) is connected with shared read and write addresses. the second function generator has the a inputs (read) connected to the second read-only port address and the w inputs (write) shared with the first read/write port address. figure 17 , figure 18 , and figure 19 illustrate various exam- ple configurations. figure 17: distributed selectram (ram16x1s) a[3:0] d d di ws wsg we wclk ram 16x1s d q ram we ck a[4:1] wg[4:1] output registered output (optional) (sr) 4 4 (by) ds031_02_100900 figure 18: single-port distributed selectram (ram32x1s) a[3:0] d wsg f5mux we wclk ram 32x1s d q we we0 ck wsf d di ws ram g[4:1] a[4] wg[4:1] d di ws ram f[4:1] wf[4:1] output registered output (optional) (sr) 4 (by) (bx) 4 ds031_03_110100
virtex-ii 1.5v field-programmable gate arrays 50 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r similar to the ram configuration, each function generator (lut) can implement a 16 x 1-bit rom. five configurations are available: rom16x1, rom32x1, rom64x1, rom128x1, and rom256x1. the rom elements are cas- cadable to implement wider or/and deeper rom. rom con- tents are loaded at configuration. table 12 shows the number of luts occupied by each configuration. shift registers each function generator can also be configured as a 16-bit shift register. the write operation is synchronous with a clock input (clk) and an optional clock enable, as shown in figure 20 . a dynamic read access is performed through the 4-bit address bus, a[3:0]. the read is asynchronous, how- ever the storage element or flip-flop is available to imple- ment a synchronous read. the storage element should always be used with a constant address. for example, when building an 8-bit shift register and configuring the addresses to point to the 7th bit, the 8th bit can be the flip- flop. the overall system performance is improved by using the superior clock-to-out of the flip-flops. an additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary lut output. (see figure 21 .) longer shift registers can be built with dynamic access to any bit in the chain. the shift register chaining and the muxf5, muxf6, and muxf7 multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one clb. figure 19: dual-port distributed selectram (ram16x1d) table 12: rom configuration rom number of luts 16 x 1 1 32 x 1 2 64 x 1 4 128 x 1 8 (1 clb) 256 x 1 16 (2 clbs) a[3:0] d wsg we wclk ram 16x1d we ck d di ws ram g[4:1] wg[4:1] dual_port ram dual_port 4 (by) dpra[3:0] spo a[3:0] wsg we ck d di ws g[4:1] wg[4:1] dpo 4 4 ds031_04_110100 (sr) figure 20: shift register configurations a[3:0] shiftin shiftout d(by) d mc15 di wsg ce (sr) clk srlc16 d q shift-reg we ck a[4:1] output registered output (optional) 4 ds031_05_110600 ws
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 51 advance product specification 1-800-255-7778 r figure 21: cascadable shift register srlc16 mc15 mc15 d srlc16 di shiftin cascadable out slice s0 slice s1 slice s2 slice s3 1 shift chain in clb clb ds031_06_110200 ff ff d srlc16 mc15 mc15 d srlc16 di shiftin shiftout ff ff d srlc16 mc15 mc15 d srlc16 di di shiftin in shiftout ff ff d srlc16 mc15 mc15 d srlc16 di shiftout ff ff d di di di out
virtex-ii 1.5v field-programmable gate arrays 52 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r multiplexers virtex-ii function generators and associated multiplexers can implement the following: 4:1 multiplexer in one slice 8:1 multiplexer in two slices 16:1 multiplexer in one clb element (4 slices) 32:1 multiplexer in two clb elements (8 slices) each virtex-ii slice has one muxf5 multiplexer and one muxfx multiplexer. the muxfx multiplexer implements the muxf6, muxf7, or muxf8, as shown in figure 22 . each clb element has two muxf6 multiplexers, one muxf7 multiplexer and one muxf8 multiplexer. examples of multiplexers are shown in the virtex-ii user manual . any lut can implement a 2:1 multiplexer. fast lookahead carry logic dedicated carry logic provides fast arithmetic addition and subtraction. the virtex-ii clb has two separate carry chains, as shown in the figure 23 . the height of the carry chains is two bits per slice. the carry chain in the virtex-ii device is running upward. the dedicated carry path and carry multiplexer (muxcy) can also be used to cascade function generators for implementing wide logic functions. figure 22: muxf5 and muxfx multiplexers slice s1 slice s0 slice s3 slice s2 clb ds031_08_110200 f5 f6 f5 f7 f5 f6 f5 f8 muxf8 combines the two muxf7 outputs (two clbs) muxf6 combines the two muxf5 outputs from slices s2 and s3 muxf7 combines the two muxf6 outputs from slices s0 and s2 muxf6 combines the two muxf6 outputs from slices s0 and s1 g f g f g f g f
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 53 advance product specification 1-800-255-7778 r arithmetic logic the arithmetic logic includes an xor gate that allows a 2-bit full adder to be implemented within a slice. in addition, a dedicated and (mult_and) gate (shown in figure 15 ) improves the efficiency of multiplier implementation. figure 23: fast carry logic path ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy cin cin cin cout ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy ff lut oi muxcy cin cout cout to cin of s2 of the next clb cout to s0 of the next clb (first carry chain) (second carry chain) slice s1 slice s0 slice s3 slice s2 clb ds031_07_110200
virtex-ii 1.5v field-programmable gate arrays 54 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r sum of products each virtex-ii slice has a dedicated or gate named orcy, oring together outputs from the slices carryout and the orcy from an adjacent slice. the orcy gate with the dedicated sum of products (sop) chain are designed for implementing large, flexible sop chains. one input of each orcy is connected through the fast sop chain to the output of the previous orcy in the same slice row. the second input is connected to the output of the top muxcy in the same slice, as shown in figure 24 . luts and muxcys can implement large and gates or other combinatorial logic functions. figure 25 illustrates lut and muxcy resources configured as a 16-input and gate. figure 24: horizontal cascade chain figure 25: wide-input and gate (12 inputs) muxcy 4 muxcy 4 slice 1 ds031_64_110300 orcy lut lut muxcy 4 muxcy 4 slice 0 v cc lut lut muxcy 4 muxcy 4 slice 3 orcy lut lut muxcy 4 muxcy 4 slice 2 v cc lut lut sop clb muxcy 4 muxcy 4 slice 1 orcy lut lut muxcy 4 muxcy 4 slice 0 v cc lut lut muxcy 4 muxcy 4 slice 3 orcy lut lut muxcy 4 muxcy 4 slice 2 v cc lut lut clb muxcy and 4 16 muxcy 4 ? 0 ? 01 01 ? 0 ? 01 ? 0 ? muxcy 4 slice out out slice lut ds031_41_110600 lut lut v cc muxcy 4 01 lut
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 55 advance product specification 1-800-255-7778 r 3-state buffers introduction each virtex-ii clb contains two 3-state drivers (tbufs) that can drive on-chip busses. each 3-state buffer has its own 3-state control pin and its own input pin. each of the four slices have access to the two 3-state buff- ers through the switch matrix, as shown in figure 26 . tbufs in neighboring clbs can access slice outputs by direct connects. the outputs of the 3-state buffers drive hor- izontal routing resources used to implement 3-state busses. the 3-state buffer logic is implemented using and-or logic rather than 3-state drivers, so that timing is more pre- dictable and less load dependant especially with larger devices. locations / organization four horizontal routing resources per clb are provided for on-chip 3-state busses. each 3-state buffer has access alternately to two horizontal lines, which can be partitioned as shown in figure 27 . the switch matrices corresponding to selectram memory and multiplier or i/o blocks are skipped. number of 3-state buffers table 13 shows the number of 3-state buffers available in each virtex-ii device. the number of 3-state buffers is twice the number of clb elements. figure 26: virtex-ii 3-state buffers slice s3 slice s2 slice s1 slice s0 switch matrix ds031_37_060700 tbuf tbuf table 13: virtex-ii 3-state buffers device 3-state buffers per row total number of 3-state buffers xc2v40 16 128 xc2v80 16 256 xc2v250 32 768 xc2v500 48 1,536 xc2v1000 64 2,560 xc2v1500 80 3,840 xc2v2000 96 5,376 xc2v3000 112 7,168 xc2v4000 144 11,520 xc2v6000 176 16,896 xc2v8000 208 23,296 xc2v10000 240 30,720 figure 27: 3-state buffer connection to horizontal lines switch matrix clb-ii switch matrix clb-ii ds031_09_032700 programmable connection 3 - state lines
virtex-ii 1.5v field-programmable gate arrays 56 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r clb/slice configurations table 14 summarizes the logic resources in one clb. all of the clbs are identical and each clb or slice can be implemented in one of the configurations listed. table 15 shows the available resources in all clbs. table 14: logic resources in one clb slices luts flip-flops mult_ands arithmetic & carry-chains sop chains distributed selectram shift registers tbuf 4 8 8 8 2 2 128 bits 128 bits 2 table 15: virtex-ii logic resources available in all clbs device clb array: row x column number of slices number of luts max distributed selectram or shift register (bits) number of flip-flops number of carry-chains 1 number of sop chains 1 xc2v40 8 x 8 256 516 8,192 516 16 16 xc2v80 16 x 8 512 1,024 16,384 1,024 16 32 xc2v250 24 x 16 1,536 3,072 49,152 3,072 32 48 xc2v500 32 x 24 3,072 6,144 98,304 6,144 48 64 xc2v1000 40 x 32 5,120 10,240 163,840 10,240 64 80 xc2v1500 48 x 40 7,680 15,360 245,760 15,360 80 96 xc2v2000 56 x 48 10,752 21,504 344,064 21,504 96 112 xc2v3000 64 x 56 14,336 28,672 458,752 28,672 112 128 xc2v4000 80 x 72 23,040 46,080 737,280 46,080 144 160 xc2v6000 96 x 88 33,792 67,584 1,081,344 67,584 176 192 xc2v8000 112 x 104 46,592 93,184 1,490,944 93,184 208 224 xc2v10000 128 x 120 61,440 122,880 1,966,080 122,880 240 256 notes: 1. the carry-chains and sop chains can be split or cascaded.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 57 advance product specification 1-800-255-7778 r 18-kbit block selectram resources introduction virtex-ii devices incorporate large amounts of 18-kbit block selectram. these complement the distributed selectram resources that provide shallow ram structures imple- mented in clbs. each virtex-ii block selectram is an 18- kbit true dual-port ram with two independently clocked and independently controlled synchronous ports that access a common storage area. both ports are functionally identical. each port has the following types of inputs: clock and clock enable, write enable, set/reset, and address, as well as separate data/parity data inputs (for write) and data/parity data outputs (for read). operation is synchronous; the block selectram behaves like a register. control, address and data inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a configuration option) clock edge. data outputs change as a result of the same clock edge. configuration the virtex-ii block selectram supports various configura- tions, including single- and dual-port ram and various data/address aspect ratios. supported memory configura- tions for single- and dual-port modes are shown in table 16 . single-port configuration as a single-port ram, the block selectram has access to the 18-kbit memory locations in any of the 2k x 9-bit, 1k x 18-bit, or 512 x 36-bit configurations and to 16-kbit memory locations in any of the 16k x 1-bit, 8k x 2-bit, or 4k x 4-bit configurations. the advantage of the 9-bit, 18-bit and 36-bit widths is the ability to store a parity bit for each eight bits. parity bits must be generated or checked exter- nally in user logic. in such cases, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. these extra parity bits are stored and behave exactly as the other bits, including the timing parameters. video applications can use the 9-bit ratio of virtex-ii block selectram memory to advantage. e ach block selectram cell is a fully synchronous memory as illustrated in figure 28 . input data bus and output data bus widths are identical. dual-port configuration as a dual-port ram, each port of block selectram has access to a common 18-kbit memory resource. these are fully synchronous ports with independent control signals for each port. the data widths of the two ports can be config- ured independently, providing built-in bus-width conversion. table 17 illustrates the different configurations available on ports a & b. table 16: dual- and single-port configurations 16k x 1 bit 2k x 9 bits 8k x 2 bits 1k x 18 bits 4k x 4 bits 512 x 36 bits figure 28: 18-kbit block selectram memory in single- port mode dop dip addr we en ssr clk 18-kbit block selectram ds031_10_102000 di do table 17: dual-port mode configurations port a 16k x 1 16k x 1 16k x 1 16k x 1 16k x 1 16k x 1 port b 16k x 1 8k x 2 4k x 4 2k x 9 1k x 18 512 x 36 port a 8k x 2 8k x 2 8k x 2 8k x 2 8k x 2 port b 8k x 2 4k x 4 2k x 9 1k x 18 512 x 36 port a 4k x 4 4k x 4 4k x 4 4k x 4 port b 4k x 4 2k x 9 1k x 18 512 x 36 port a 2k x 9 2k x 9 2k x 9 port b 2k x 9 1k x 18 512 x 36 port a 1k x 18 1k x 18 port b 1k x 18 512 x 36 port a 512 x 36 port b 512 x 36
virtex-ii 1.5v field-programmable gate arrays 58 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r if both ports are configured in either 2k x 9-bit, 1k x 18-bit, or 512 x 36-bit configurations, the 18-kbit block is accessi- ble from port a or b. if both ports are configured in either 16k x 1-bit, 8k x 2-bit. or 4k x 4-bit configurations, the 16 k- bit block is accessible from port a or port b. all other con- figurations result in one port having access to an 18-kbit memory block and the other port having access to a 16 k-bit subset of the memory block equal to 16 kbits. each block selectram cell is a fully synchronous memory, as illustrated in figure 29 . the two ports have independent inputs and outputs and are independently clocked. port aspect ratios table 18 shows the depth and the width aspect ratios for the 18-kbit block selectram. virtex-ii block selectram also includes dedicated routing resources to provide an efficient interface with clbs, block selectram, and multipliers. read/write operations the virtex-ii block selectram read operation is fully syn- chronous. an address is presented, and the read operation is enabled by control signal ena or enb. then, depending on clock polarity, a rising or falling clock edge causes the stored data to be loaded into output registers. the write operation is also fully synchronous. data and address are presented, and the write operation is enabled by control signals wea or web in addition to ena or enb. then, again depending on the clock input mode, a rising or falling clock edge causes the data to be loaded into the memory cell addressed. a write operation performs a simultaneous read operation. there are three different options are available, each set by configuration: 1. ? write_first ? the ? write_first ? option is a transparent mode. the same clock edge that writes the data input (di) into the memory also transfers di into the output registers do as shown in figure 30 . figure 29: 18 - kbit block selectram in dual-port mode dopa dopb dipa addra wea ena ssra clka dipb addrb web enb ssrb clkb 18-kbit block selectram ds031_11_102000 dob doa dia dib table 18: 18 - kbit block selectram port aspect ratio width depth address bus data bus parity bus 1 16,384 addr[13:0] data[0] n/a 2 8,192 addr[12:0] data[1:0] n/a 4 4,096 addr[11:0] data[3:0] n/a 9 2,048 addr[10:0] data[7:0] parity[0] 18 1,024 addr[9:0] data[15:0] parity[1:0] 36 512 addr[8:0] data[31:0] parity[3:0] figure 30: write_first mode clk we data_in data_in new aa address internal memory do data_out = data_in data_out di ds031_14_102000 new ram contents new old
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 59 advance product specification 1-800-255-7778 r 2. ? read_first ? the ? read_first ? option is a read-before-write mode. the same clock edge that writes data input (di) into the memory also transfers the prior content of the memory cell addressed into the data output registers do, as shown in figure 31 . 3. ? no_change ? the ? no_change ? option maintains the content of the output registers, regardless of the write operation. the clock edge during the write mode has no effect on the content of the data output register do. when the port is configured as ? no_change ? , only a read operation loads a new value in the output register do, as shown in figure 32 . figure 31: read_first mode clk we data_in data_in new aa old address internal memory do prior stored data data_out di ds031_13_102000 ram contents new old figure 32: no_change mode clk we data_in data_in new aa last read cycle content (no change) address internal memory do no change during write data_out di ds031_12_102000 ram contents new old
virtex-ii 1.5v field-programmable gate arrays 60 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r control pins and attributes virtex-ii selectram memory has two independent ports with the control signals described in table 19 . all control inputs including the clock have an optional inversion. initial memory content is determined by the init_xx attributes. separate attributes determine the output register value after device configuration (init) and ssr is asserted (srval). both attributes (init_b and srval) are available for each port when a block selectram resource is config- ured as dual-port ram. locations virtex-ii selectram memory blocks are organized in either four or six columns. the number of blocks per column depends of the device array size and is equivalent to the number of clbs in a column divided by four. column loca- tions are shown in table 20 . table 19: control functions control signal function clk read and write clock en enable affects read, write, set, reset we write enable ssr set do register to srval (attribute) table 20: selectram memory floor plan device columns selectram blocks per column total xc2v40 2 2 4 xc2v80 2 4 8 xc2v250 4 6 24 xc2v500 4 8 32 xc2v1000 4 10 40 xc2v1500 4 12 48 xc2v2000 4 14 56 xc2v3000 6 16 96 xc2v4000 6 20 120 xc2v6000 6 24 144 xc2v8000 6 28 168 xc2v10000 6 32 192 figure 33: block selectram (2-column, 4-column, and 6-column) 2 clb columns 2 clb columns 2 clb columns n clb columns 2 clb columns n clb columns 2 clb columns 2 clb columns 2 clb columns n clb columns n clb columns n clb columns 2 clb columns n clb columns selectram blocks selectram blocks ds031_38_101000 2 clb column 2 clb columns selectram blocks 2 clb column 2 clb columns
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 61 advance product specification 1-800-255-7778 r total amount of selectram memory table 21 shows the amount of block selectram memory available for each virtex-ii device. the 18-kbit selectram blocks are cascadable to implement deeper or wider single- or dual-port memory resources. table 21: virtex-ii selectram memory available device total selectram memory blocks in kbits in bits xc2v40 4 72 73,728 xc2v80 8 144 147,456 xc2v250 24 432 442,368 xc2v500 32 576 589,824 xc2v1000 40 720 737,280 xc2v1500 48 864 884,736 xc2v2000 56 1,008 1,032,192 xc2v3000 96 1,728 1,769,472 xc2v4000 120 2,160 2,211,840 xc2v6000 144 2,592 2,654,208 xc2v8000 168 3,024 3,096,576 xc2v10000 192 3,456 3,538,944
virtex-ii 1.5v field-programmable gate arrays 62 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r 18-bit x 18-bit multipliers introduction a virtex-ii multiplier block is an 18-bit by 18-bit 2 ? s comple- ment signed multiplier. virtex-ii devices incorporate many embedded multiplier blocks. these multipliers can be asso- ciated with an 18-kbit block selectram resource or can be used independently. they are optimized for high-speed operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices. each selectram memory and multiplier block is tied to four switch matrices, as shown in figure 34 . association with block selectram memory the interconnect is designed to allow selectram memory and multiplier blocks to be used at the same time, but some interconnect is shared between the selectram and the multiplier. thus, selectram memory can be used only up to 18 bits wide when the multiplier is used, because the multi- plier shares inputs with the upper data bits of the selectram memory. this sharing of the interconnect is optimized for an 18-bit- wide block selectram resource feeding the multiplier. the use of selectram memory and the multiplier with an accu- mulator in luts allows for implementation of a digital signal processor (dsp) multiplier-accumulator (mac) function, which is commonly used in finite and infinite impulse response (fir and iir) digital filters. configuration the multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). both a and b are 18-bit-wide inputs, and the output is 36 bits. figure 35 shows a multiplier block. locations / organization multiplier organization is identical to the 18-kbit selectram organization, because each multiplier is associated with an 18-kbit block selectram resource. figure 34: selectram and multiplier blocks switch matrix switch matrix 18-kbit block selectram 18 x 18 multiplier switch matrix switch matrix ds031_33_101000 figure 35: multiplier block table 22: multiplier floor plan device columns multipliers per column total xc2v40 2 2 4 xc2v80 2 4 8 xc2v250 4 6 24 xc2v500 4 8 32 xc2v1000 4 10 40 xc2v1500 4 12 48 xc2v2000 4 14 56 xc2v3000 6 16 96 xc2v4000 6 20 120 xc2v6000 6 24 144 xc2v8000 6 28 168 xc2v10000 6 32 192 mult 18 x 18 a[17:0] p[35:0] b[17:0] multiplier block ds031_40_061400
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 63 advance product specification 1-800-255-7778 r in addition to the built-in multiplier blocks, the clb elements have dedicated logic to implement efficient multipliers in logi c. (refer to "configurable logic blocks (clbs)" on page 46 ). figure 36: multipliers (4 column vs. 6 column) ds031_39_101000 2 clb columns 2 clb columns 2 clb columns n clb columns 2 clb columns n clb columns 2 clb columns 2 clb columns 2 clb columns n clb columns n clb columns n clb columns 2 clb columns n clb columns multiplier blocks multiplier blocks 2 clb column 2 clb columns multiplier blocks 2 clb column 2 clb columns
virtex-ii 1.5v field-programmable gate arrays 64 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r global clock multiplexer buffers virtex-ii devices have 16 clock input pins that can also be used as regular user i/os. eight clock pads are on the top edge of the device, in the middle of the array, and eight are on the bottom edge, as illustrated in figure 37 . the global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in virtex-ii devices. like the clock pads, eight global clock multiplexer buffers are on the top edge of the device and eight are on the bottom edge. each global clock buffer can either be driven by the clock pad to distribute a clock directly to the device, or driven by the digital clock manager (dcm), discussed in "digital clock manager (dcm)" on page 66 . each global clock buffer can also be driven by local interconnects. the dcm has clock output(s) that can be connected to global clock buffer inputs, as shown in figure 38 . global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in clbs and iobs, and selectram blocks. eight global clocks can be used in each quadrant of the virtex-ii device. designers should consider the clock distri- bution detail of the device prior to pin-locking and floorplan- ning (see the virtex-ii user manual ). figure 39 shows clock distribution in virtex-ii devices. figure 37: virtex-ii clock pads 8 clock pads 8 clock pads virtex-ii device ds031_42_101000 figure 38: virtex-ii clock distribution configurations clock pad clock buffer i 0 clock distribution clock pad clock buffer i 0 clock distribution clkin clkout dcm ds031_43_101000 figure 39: virtex-ii clock distribution 8 8 8 8 nw nw ne sw se ne sw se ds031_45_101600 8 bufgmux 8 bufgmux 8 max 8 bufgmux 8 bufgmux 16 clocks 16 clocks
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 65 advance product specification 1-800-255-7778 r in each quadrant, up to eight clocks are organized in clock rows. a clock row supports up to 16 clb rows (eight up and eight down). for the largest devices a new clock row is added, as necessary. to reduce power consumption, any unused clock branches remain static. the global clock multiplexer buffers have two clock inputs, a select input, and a clock output. the select input selects between i o and i 1 without generating glitches. the most common configuration option of this element is as a buffer. a bufg function in this (global buffer) mode, is shown in figure 40 . in figure 41 the global buffer can also perform a clock enable function (clock gating). the ce input is synchro- nized inside the bufg so any change in ce is only effective when the clock input is low. this eliminates any glitches or runt pulses on the output, even when ce changes asyn- chronously to the clock. the two clock inputs can be connected to any synchronous or asynchronous clock (from a clock pad or dcm clock out- put). when the select input (s) is low, the clock connected to the i 0 input is distributed, as shown in figure 42 . setting s high, causes the clock connected to the i 1 input to be dis- tributed. the clock multiplexer can also switch between two unre- lated clocks. the s input can be changed asynchronously to both clocks. internal synchronization switches away for the present clock when it is low but switches to the new clock only after the subsequent falling edge. when s changes state, the transition on the output occurs without creating a runt pulse. the output pulse is never shorter than the i 0 or i 1 input pulse. the s input has a setup requirement. the global clock multiplexer buffers has two options: transition on low clock states transition on high clock states the transition on low follows different steps, as illustrated in figure 43 . the current clock is clk0. s is activated high (setup is required before the next negative clk0 edge). if clk0 is currently high, the multiplexer waits for the next negative edge. once clk0 is low, the multiplexer output stays low, until clk1 goes low. when clk1 transitions from high to low, the output switches to clk1. no glitches or short pulses can appear on the output. the transition on high clock state is similar, with the positive edge of the second clock low. all virtex-ii devices have 16 global clock multiplexer buffers. figure 40: virtex-ii bufg function figure 41: virtex-ii bufgce function o i bufg ds031_61_101200 o i ce bufgce ds031_62_101200 figure 42: virtex-ii bufgmux function figure 43: clock multiplexer waveform diagram o i0 i1 s bufgmux ds031_63_112900 s clk0 clk1 out wait for low switch ds031_46_112900
virtex-ii 1.5v field-programmable gate arrays 66 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r digital clock manager (dcm) the virtex-ii dcm offers a wide range of powerful clock management features. clock de-skew : the dcm generates new system clocks (either internally or externally to the fpga), which are phase-aligned to the input clock. frequency synthesis : the dcm generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. phase shifting : the dcm provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control. emi reduction : the dcm provides the capability to reduce electromagnetic interference (emi) by broadening the output clock frequency spectrum. the dcm utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. it also utilizes fully digital feedback systems, operating dynami- cally to compensate for temperature and voltage variations during operation. up to four dcm clock outputs can drive global clock multi- plexer buffer inputs simultaneously (see figure 44 ). all dcm clock outputs can simultaneously drive general rout- ing resources, including routes to output buffers. the dcm can be configured to delay the completion of the virtex-ii configuration process until after the dcm has achieved lock. this guarantees that the chip does not begin operating until after the system clocks generated by the dcm have stabilized. the dcm has the following general control signals: rst input pin : resets the entire dcm locked output pin: asserted high when all enabled dcm circuits have locked. status output pins (active high): shown in table 1 . clock de-skew the dcm de-skews the output clocks relative to the input clock by automatically adjusting a digital delay line. addi- tional delay is introduced so that clock edges arrive at inter- nal registers and block ram synchronous to clock edges arriving at the input. alternatively, external clocks, which are also de-skewed relative to the input clock, can be generated for board-level routing. all dcm output clocks are phase- aligned to clk0 and, therefore, are also phase-aligned to the input clock. to achieve clock de-skew, the clkfb input must be con- nected, and its source must be either clk0 or clk2x. note that clkfb must always be connected, unless only the clkfx or clkfx180 outputs are used and de-skew is not required. frequency synthesis the dcm provides flexible methods for generating new clock frequencies. each method has a different operating frequency range and different ac characteristics. the clk2x and clk2x180 outputs can be used to double the clock fre- quency. the clkdv output can be used to create divided out- put clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. the clkfx and clkfx180 outputs can be used to pro- duce clocks at the following frequency: freq clkfx = (m/d) * freq clkin where m and d are two integers, each between 1 and 4096. by default, m=4 and d=1, which results in a clock output frequency four times faster than the clock input frequency (clkin). clk2x180 is phase shifted 180 degrees relative to clk2x. clkfx180 is phase shifted 180 degrees relative to clkfx. all frequency synthesis outputs automatically have 50/50 duty cycles (with the exception of the clkdv output when performing a non-integer divide in high frequency mode). figure 44: digital clock manager clkin clkfb clk180 clk270 clk0 clk90 clk2x clk2x180 clkdv dcm ds031_67_112900 clkfx clkfx180 locked status[7:0] psdone rst dssen psincdec psen psclk clock signal control signal table 23: dcm status pins status pin function 0 phase shift overflow 1 clkin stopped 2n/a 3n/a 4n/a 5n/a 6n/a 7n/a
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 67 advance product specification 1-800-255-7778 r phase shifting the dcm provides additional control over clock skew through either coarse or fine-grained phase shifting. the clk0, clk90, clk180, and clk270 outputs are each phase shifted by ? of the input clock period relative to each other, allowing coarse phase adjustments. fine phase adjustment applies to all dcm output clocks when activated. the phase shift between the rising edges of clkin and clkfb is configured to be a specified fraction of the input clock period, and it can be dynamically adjusted with the dedicated signals, psincdec, psen, psclk, and psdone. the phase shift value (ps) is specified as an integer between ? 255 and +255. the amount of phase shift achieved is given by the equation: phase shift = (ps/256) * period clkin in variable mode, the ps value can be dynamically incre- mented or decremented according to psincdec synchro- nously to psclk, when the psen input is active. figure 45 illustrates the effects of fine phase shifting. table 24 lists fine phase shifting control pins, when used in variable mode. emi reduction the dcm offers a digital spread spectrum (dss) feature that broadens the frequency spectrum of the clock outputs. the spectrum spreading applies directly to the clk0, clk90, clk180, and clk270 clock outputs when it is active. the other dcm clock outputs are affected to only a small degree. spreading the spectrum of the clock fre- quency reduces the electromagnetic interference (emi), or energy radiation, within the relevant frequency bandwidth window. this technique aids in meeting fcc emi regula- tions. when enabled, spectrum spreading begins immediately after the locked signal goes high. the dssen input can be used to enable/disable the feature during operation. table 25 lists available dss options. . table 24: fine phase shifting control pins control pin direction function psincdec in increment or decrement psen in enable phase shift psclk in clock for phase shift psdone out active when completed figure 45: fine phase shifting effects clkout_phase_shift = fixed clkout_phase_shift = variable clkout_phase_shift = none clkin clkfb clkin clkin clkfb (ps/256) x period clkin (ps negative) (ps/256) x period clkin (ps positive) clkfb (ps/256) x period clkin (ps negative) (ps/256) x period clkin (ps positive) ds031_48_110300 table 25: dss options number of frequencies added mode clock period range 2 spread_2 1 x dcm_tap 4 spread_4 2 x dcm_tap 6 spread_6 3 x dcm_tap 8 spread_8 4 x dcm_tap notes: 1. dcm _tap value is defined in the ac characteristics section
virtex-ii 1.5v field-programmable gate arrays 68 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r operating modes the frequency ranges of the dcm input and output clocks depend on the operating mode specified, either low frequency mode or high frequency mode, according to table 26 (for actual values, see "virtex-ii switching characteristics" on page 81 ). the clk2x, clk2x180, clk90, and clk270 outputs are not available in high frequency mode. locations/organization virtex-ii dcms are placed on the top and bottom of each block ram and multiplier column. the number of dcms depends on the device size, as shown in table 27 . table 26: dcm frequency ranges output clock low-frequency mode high-frequency mode clkin input clk output clkin input clk output clk0, clk180 clkin_freq_dll_lf clkout_freq_1x_lf clkin_freq_dll_hf clkout_freq_1x_hf clk90, clk270 clkin_freq_dll_lf clkout_freq_1x_lf na na clk2x, clk2x180 clkin_freq_dll_lf clkout_freq_2x_lf na na clkdv clkin_freq_dll_lf clkout_freq_dv_lf clkin_freq_dll_hf clkout_freq_dv_hf clkfx, clkfx180 clkin_freq_fx_lf clkout_freq_fx_lf clkin_freq_fx_hf clkout_freq_fx_hf table 27: dcm organization device columns dcms xc2v40 2 4 xc2v80 2 4 xc2v250 4 8 xc2v500 4 8 xc2v1000 4 8 xc2v1500 4 8 xc2v2000 4 8 xc2v3000 6 12 xc2v4000 6 12 xc2v6000 6 12 xc2v8000 6 12 xc2v10000 6 12
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 69 advance product specification 1-800-255-7778 r active interconnect technology local and global virtex-ii routing resources are optimized for speed and timing predictability, as well as to facilitate ip cor es implementation. virtex-ii active interconnect technology is a fully buffered programmable routing matrix. all routing resources are segmented to offer the advantages of a hierarchical solution. virtex-ii logic features like clbs, iobs, block ram, multipliers, and dcms are all connected to an identical switch matrix for access to global routing resources, as shown in figure 46 . each virtex-ii device can be represented as an array of switch matrixes with logic blocks attached, as illustrated in figure 47 . figure 46: active interconnect technology figure 47: routing resources switch matrix switch matrix switch matrix switch matrix switch matrix clb 18kb bram mult 18 x 18 switch matrix iob switch matrix dcm ds031_55_101000 switch matrix iob switch matrix iob switch matrix iob switch matrix dcm switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix selectram multiplier ds031_34_110300
virtex-ii 1.5v field-programmable gate arrays 70 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r place-and-route software takes advantage of this regular array to deliver optimum system performance and fast com- pile times. the segmented routing resources are essential to guarantee ip cores portability and to efficiently handle an incremental design flow that is based on modular imple- mentations. total design time is reduced due to fewer and shorter design iterations. hierarchical routing resources most virtex-ii signals are routed using the global routing resources, which are located in horizontal and vertical rout- ing channels between each switch matrix. as shown in figure 47 , virtex-ii has fully buffered program- mable interconnections, with a number of resources counted between any two adjacent switch matrix rows or columns. fanout has minimal impact on the performance of each net. the long lines are bidirectional wires that distribute signals across the device. vertical and horizontal long lines span the full height and width of the device. the hex lines route signals to every third or sixth block away in all four directions. organized in a staggered pattern, hex lines can only be driven from one end. hex- line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). the double lines route signals to every first or second block away in all four directions. organized in a staggered pattern, double lines can be driven only at their endpoints. double-line signals can be accessed either at the endpoints or at the midpoint (one block from the source). the direct connect lines route signals to neighboring blocks: vertically, horizontally, and diagonally. the fast connect lines are the internal clb local interconnections from lut outputs to lut inputs. dedicated routing in addition to the global and local routing resources, dedi- cated signals are available. there are eight global clock nets per quadrant (see global clock multiplexer buffers ). horizontal routing resources are provided for on-chip 3-state busses. four partitionable bus lines are provided per clb row, permitting multiple busses within a row. (see 3-state buffers .) two dedicated carry-chain resources per slice column (two per clb column) propagate carry-chain muxcy output signals vertically to the adjacent slice. (see clb/slice configurations .) one dedicated sop chain per slice row (two per clb row) propagate orcy output logic signals horizontally to the adjacent slice. (see sum of products .) figure 48: hierarchical routing resources 24 horizontal long lines 24 vertical long lines 120 horizontal hex lines 120 vertical hex lines 40 horizontal double lines 40 vertical double lines 16 direct connections (total in all four directions) 8 fast connects ds031_60_110200
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 71 advance product specification 1-800-255-7778 r one dedicated shift-chain per clb connects the output of luts in shift-register mode to the input of the next lut in shift-register mode (vertically) inside the clb. (see "shift registers" on page 50 .) creating a design creating virtex-ii designs is easy with xilinx development systems, supporting advanced design capabilities including incremental synthesis, modular design, integrated logic analysis, and the fastest place and route runtimes in the industry. this means designers get the performance they need, quickly. as a result of the ongoing cooperative development efforts between xilinx and eda alliance partners, designers can take advantage of the benefits provided by eda technolo- gies in the programmable logic design process. xilinx devel- opment systems are available in a number of easy to use configurations within the alliance series and foundation series product families. alliance series solutions alliance series solutions are designed to plug and play within a chosen design environment. built using industry standard data formats and netlists, these stable, flexible products also enable alliance eda partners to deliver their best design automation capabilities to xilinx customers, pro- viding incremental synthesis, modular design, and error nav- igation -- all features developed with xilinx eda partners, for use with xilinx development systems first. foundation series solutions foundation series solutions feature foundation integrated synthesis environment (ise) tools, a family of products that deliver all of the benefits of true hdl-based design in a seamlessly integrated design environment. an intuitive project navigator, as well as powerful hdl design and two hdl synthesis tools, ensure that high-quality results are achieved quickly and easily. the foundation ise product includes: state diagram entry using statecad xe automatic hdl testbench generation using hdlbencher xe hdl simulation using modelsim xe-starter (mxe-starter). mxe starter is particularly useful in demonstrating the seamless integration available between the ise design environment and modelsim hdl simulation tools. design flow virtex-ii design flow proceeds as follows: design entry synthesis implementation verification most programmable logic designers iterate through these steps several times in the process of completing a design. design entry xilinx development systems support the mainstream eda design entry capabilities, ranging from schematic design to advanced hdl design methodologies. given the high densi- ties of the virtex-ii family, designs are most efficiently cre- ated using hdls. to improve efficiency, many xilinx customers employ incremental, modular, and intellectual property (ip) design techniques. when properly used, these techniques further accelerate the logic design process. to enable designers to leverage existing investments in eda tools, and to ensure high performance design flows, xilinx jointly develops tools with leading eda vendors, including: aldec cadence exemplar mentor graphics model technology synopsys synplicity vss complete information on alliance series partners and their associated design flows is available from the xilinx alliance series web page: www. xilinx .com/products/alliance.htm xilinx foundation series products offer schematic entry and hdl design capabilities as part of an integrated design solu- tion - enabling one-stop shopping. these capabilities are powerful, easy to use, and they support the full portfolio of xilinx programmable logic devices. hdl design capabilities include a color-coded hdl editor with integrated language templates, state diagram entry, and core generation capa- bilities. synthesis alliance series products are engineered to support advanced design flows with the industry's best synthesis tools for: incremental synthesis rtl floorplanning automated timing convergence direct physical mapping the xilinx foundation ise product family includes synthesis capabilities from both fpga express and a proprietary syn- thesis tool referred to as xilinx synthesis technology. having two seamlessly integrated synthesis engines within the foun- dation ise products provides an alternative set of optimization
virtex-ii 1.5v field-programmable gate arrays 72 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r techniques for designs, helping to ensure that foundation ise can meet even the toughest timing requirements. both fpga express and xilinx synthesis technology sup- port the synthesis of vhdl and verilog; however, only fpga express enables mixed-language synthesis. future releases of the ise design environment are planned to also integrate other third party synthesis tools, like synplicity synplify and exemplar's leonardo spectrum. design implementation the alliance series and foundation series development systems both include xilinx timing-driven implementation tools, frequently called ? place and route ? software. this robust suite of tools enables the creation of an intuitive, flex- ible, tightly integrated design flow that efficiently bridges the ? logical ? and ? physical ? design domains. this simplifies the task of defining a design, including its behavior, timing requirements, and optional layout (or floorplanning), as well as simplifying the task of analyzing reports generated during the implementation process. the virtex-ii implementation process is comprised of syn- thesis, translation, mapping, place and route, and configura- tion file generation. while the tools can be run individually, many designers choose to run the entire implementation process with the click of a button. to assist those who prefer to script their design flows, xilinx provides xflow, an auto- mated single command line process. design verification in addition to conventional design verification using static timing analysis or dynamic timing analysis (simulation), pow- erful in-circuit debugging techniques using xilinx chipscope ila (integrated logic analysis) is available. in these recon- figurable xilinx fpgas, designs can be verified in real time without the need for extensive sets of software simulation vectors. the development system supports both software simulation and in-circuit debugging techniques. for simulation, the system extracts post-layout timing infor- mation from the design database, and back-annotates this information into the netlist for use by the simulator. the back annotation features a variety of patented xilinx techniques, resulting in the industry ? s most powerful simulation flows. alternatively, the user can verify timing-critical portions of a design using the trce ? static timing analyzer, or using a third party static timing analysis tool by exporting timing data in the stamp data format. for in-circuit debugging, chipscope ila enables designers to analyze the real-time behavior of a device while operat- ing at full system speeds. logic analysis commands and captured data are transferred between the chipscope soft- ware and ila cores within the virtex-ii fpga, using industry standard jtag protocols. these jtag transactions are driven over an optional download cable (multilinx or jtag), connecting the virtex device in the target system to a pc or workstation. chipscope ila was designed to look and feel like a logic analyzer, making it easy to begin debugging a design immediately. modifications to the desired logic analysis can be downloaded into the system in a matter of minutes. other unique features of virtex-ii design flow xilinx design flows feature a number of unique capabilities. among these are efficient incremental hdl design flows; a robust capability that is enabled by xilinx exclusive hierarchi- cal floorplanning capabilities. another powerful design capa- bility only available in the xilinx design flow is ? modular design ? , part of the xilinx suite of team design tools, which enables autonomous design, implementation, and verifica- tion of design modules. incremental synthesis xilinx unique hierarchical floorplanning capabilities enable designers to create a programmable logic design by isolat- ing design changes within one hierarchical ? logic block ? , and perform synthesis, verification and implementation pro- cesses on that specific logic block. by preserving the logic in unchanged portions of a design, xilinx incremental design makes the high-density design process more efficient. xilinx hierarchical floorplanning capabilities can be specified using the high-level floorplanner or a preferred rtl floor- planner (see the xilinx web site for a list of supported eda partners). when used in conjunction with one of the eda partners ? floorplanners, higher performance results can be achieved, as many synthesis tools use this more predictable detailed physical implementation information to establish more aggressive and accurate timing estimates when per- forming their logic optimizations. modular design xilinx innovative modular design capabilities take the incre- mental design process one step further by enabling the designer to delegate responsibility for completing the design, synthesis, verification, and implementation of a hier- archical ? logic block ? to an arbitrary number of designers - assigning a specific region within the target fpga for exclu- sive use by each of the team members. this team design capability enables an autonomous approach to design modules, changing the hand-off point to the lead designer or integrator from ? my module works in simulation ? to ? my module works in the fpga ? . this unique design methodology also leverages the xilinx hierarchical floorplanning capabilities and enables the xilinx (or eda partner) floorplanner to manage the efficient implementation of very high-density fpgas.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 73 advance product specification 1-800-255-7778 r configuration virtex-ii devices are configured by loading application spe- cific configuration data into the internal configuration mem- ory. configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re- used as general purpose inputs and outputs once configu- ration is complete. depending on the system design, several configuration modes are supported, selectable via mode pins. the mode pins m2, m1 and m0 are dedicated pins. an additional pin, hswap_en is used in conjunction with the mode pins to select whether user i/o pins have pull-ups during configura- tion. by default, hswap_en is tied high (internal pull-up) which shuts off the pull-ups on the user i/o pins during con- figuration. when hswap_en is tied low, user i/os have pull-ups during configuration. other dedicated pins are cclk (the configuration clock pin), done, prog_b, and the boundary-scan pins: tdi, tdo, tms, and tck. depending on the configuration mode chosen, cclk can be an output generated by the fpga, or an input accepting an externally generated clock. the configuration pins and boundary scan pins are independent of the v cco . the aux- iliary power supply (v ccaux ) of 3.3v is used for these pins. (see "virtex-ii dc characteristics" on page 76 .) a persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. if the persist option is not selected then the configuration pins with the exception of cclk, prog_b, and done can be used as user i/o in normal operation. the persist option does not apply to the boundary-scan related pins. the persist feature is valuable in applications which employ partial reconfiguration or reconfiguration on the fly. configuration modes virtex-ii supports the following five configuration modes: slave-serial mode master-serial mode slave selectmap mode master selectmap mode boundary-scan mode (ieee 1532/ieee 1149) a detailed description of configuration modes is provided in the virtex-ii user manual . slave-serial mode in slave-serial mode, the fpga receives configuration data in bit-serial form from a serial prom or other serial source of configuration data. the cclk pin on the fpga is an input in this mode. the serial bitstream must be setup at the din input pin a short time before each rising edge of the externally generated cclk. multiple fpgas can be daisy-chained for configuration from a single source. after a particular fpga has been config- ured, the data for the next device is routed internally to the dout pin. the data on the dout pin changes on the rising edge of cclk. slave-serial mode is selected by applying <111> to the mode pins (m2, m1, m0). a weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. master-serial mode in master-serial mode, the cclk pin is an output pin. it is the virtex-ii fpga device that drives the configuration clock on the cclk pin to a xilinx serial prom which in turn feeds bit-serial data to the din input. the fpga accepts this data on each rising cclk edge. after the fpga has been loaded, the data for the next device in a daisy-chain is pre- sented on the dout pin after the rising cclk edge. the interface is identical to slave serial except that an inter- nal oscillator is used to generate the configuration clock (cclk). a wide range of frequencies can be selected for cclk which always starts at a slow default frequency. con- figuration bits then switch cclk to a higher frequency for the remainder of the configuration. slave selectmap mode the selectmap mode is the fastest configuration option. byte-wide data is written into the virtex-ii fpga device with a busy flag controlling the flow of data. an external data source provides a byte stream, cclk, an active low chip select (cs_b) signal and a write signal (rdwr_b). if busy is asserted (high) by the fpga, the data must be held until busy goes low. data can also be read using the selectmap mode. if rdwr_b is asserted, configuration data is read out of the fpga as part of a readback opera- tion. after configuration, the pins of the selectmap port can be used as additional user i/o. alternatively, the port can be retained to permit high-speed 8-bit readback using the per- sist option. multiple virtex-ii fpgas can be configured using the selectmap mode, and be made to start-up simultaneously. to configure multiple devices in this way, wire the individual cclk, data, rdwr_b, and busy pins of all the devices in parallel. the individual devices are loaded separately by deasserting the cs_b pin of each device in turn and writing the appropriate data. master selectmap mode this mode is a master version of the selectmap mode. the device is configured byte-wide on a cclk supplied by the virtex-ii fpga device. timing is similar to the slave serialmap mode except that cclk is supplied by the virtex-ii fpga.
virtex-ii 1.5v field-programmable gate arrays 74 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r boundary-scan (jtag, ieee 1532) mode in boundary-scan mode, dedicated pins are used for configur- ing the virtex-ii device. the configuration is done entirely through the ieee 1149.1 test access port (tap). virtex-ii device configuration using boundary scan is compliant with ieee 1149.1-1993 standard and the new ieee 1532 standard for in-system configurable (isc) devices. the ieee 1532 standard is backward compliant with the ieee 1149.1-1993 tap and state machine. the ieee standard 1532 for in-sys- tem configurable (isc) devices is intended to be pro- grammed, reprogrammed, or tested on the board via a physical and logical protocol. configuration through the boundary-scan port is always available, independent of the mode selection. selecting the boundary-scan mode simply turns off the other modes. table 29 lists the total number of bits required to configure each device. configuration sequence the configuration of virtex-ii devices is a three-phase pro- cess. first, the configuration memory is cleared. next, con- figuration data is loaded into the memory, and finally, the logic is activated by a start-up process. configuration is automatically initiated on power-up unless it is delayed by the user. the init_b pin can be held low using an open-drain driver. an open-drain is required since init_b is a bidirectional open-drain pin that is held low by a virtex-ii fpga device while the configuration memory is being cleared. extending the time that the pin is low causes the configuration sequencer to wait. thus, configuration is delayed by prevent- ing entry into the phase where data is loaded. the configuration process can also be initiated by asserting the prog_b pin. the end of the memory-clearing phase is signaled by the init_b pin going high, and the completion of the entire process is signaled by the done pin going high. the global set/reset (gsr) signal is pulsed after the last frame of configuration data is written but before the start-up sequence. the gsr signal resets all flip-flops on the device. the default start-up sequence is that one cclk cycle after done goes high, the global 3-state signal (gts) is released. this permits device outputs to turn on as neces- sary. one cclk cycle later, the global write enable (gwe) signal is released. this permits the internal storage ele- ments to begin changing state in response to the logic and the user clock. the relative timing of these events can be changed via con- figuration options in software. in addition, the gts and gwe events can be made dependent on the done pins of multiple devices all going high, forcing the devices to start synchronously. the sequence can also be paused at any stage, until lock has been achieved on any or all dcms, as well as the dci. table 28: virtex-ii configuration mode pin settings configuration mode 1 m2 m1 m0 cclk direction data width serial d out 2 master serial 0 0 0 out 1 yes slave serial 1 1 1 in 1 yes master selectmap 0 1 1 out 8 no slave selectmap 1 1 0 in 8 no boundary scan 1 0 1 n/a 1 no notes: 1. the hswap_en pin controls the pullups. setting m2, m1, and m0 selects the configuration mode, while the hswap_en pin controls whether or not the pullups are used. 2. daisy chaining is possible only in modes where serial d out is used. for example, in selectmap modes, the first device does not support daisy chaining of downstream devices. table 29: virtex-ii bitstream lengths device # of configuration bits xc2v40 338,208 xc2v80 597,408 xc2v250 1,591,584 xc2v500 2,557,856 xc2v1000 3,749,408 xc2v1500 5,166,240 xc2v2000 6,808,352 xc2v3000 9,589,408 xc2v4000 14,220,192 xc2v6000 19,752,096 xc2v8000 26,185,120 xc2v10000 33,519,264
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 75 advance product specification 1-800-255-7778 r readback in this mode, configuration data from the virtex-ii fpga device can be read back. readback is supported only in the selectmap (master and slave) and boundary scan mode. along with the configuration data, it is possible to read back the contents of all registers, distributed selectram, and block ram resources. this capability is used for real-time debugging. for more detailed configuration information, see the virtex-ii user manual. bitstream encryption virtex-ii devices have an on-chip decryptor using one or two sets of three keys for triple-key data encryption standard (des) operation. xilinx software tools offer an optional encryption of the configuration data (bitstream) with a triple- key des determined by the designer. the keys are stored in the fpga by jtag instruction and retained by a battery connected to the v batt pin, when the device is not powered. virtex-ii devices can be configured with the corresponding encrypted bitstream, using any of the configuration modes described previously. a detailed description of how to use bitstream encryption is provided in the virtex-ii user manual . partial reconfiguration partial reconfiguration of virtex-ii devices can be accom- plished in either slave selectmap mode or boundary-scan mode. instead of resetting the chip and doing a full configu- ration, new data is loaded into a specified area of the chip, while the rest of the chip remains in operation. data is loaded on a column basis, with the smallest load unit being a configuration ? frame ? of the bitstream (device size depen- dent). partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, or that require the ability to change portions of a design without having to reset or reconfigure the entire chip. power-down sequence the power-down sequence enables a designer to set the device into a low-power, inactive state. the sequence is ini- tiated by pulling the pwrdwn_b pin low. if the pwrdwn_stat option is selected using bitgen, the done pin can serve as the power-down status pin. when asserted, power-down has completed. after a successful wake-up, the status pin deasserts. while powered down, the only active pins are the pwrdwn_b and done. all inputs are off and all outputs are 3-stated. while in the powerdown state, the power on reset (por) circuit is still active, but it does not reset the device if v ccint , v cco , or v ccaux falls below its minimum value. the por circuit waits until the pwrdwn_b pin is released before resetting the device. also, the prog_b pin is not sampled while the device is in the powerdown state. the prog_b pin becomes active when the pwrdwn_b pin is released. therefore, the device cannot be reset while in the powerdown state. the wake-up sequence is the reverse of the power-down sequence.
virtex-ii 1.5v field-programmable gate arrays 76 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r virtex-ii electrical characteristics virtex-ii devices are provided in -4, -5, and -6 speed grades, with -6 having the highest performance. virtex-ii dc and ac characteristics are specified for both commercial and industrial grades. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -4 speed grade industrial device are the same as for a -4 speed grade commercial device). however, only selected speed grades and/or devices might be available in the industrial range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parame- ters included are common to popular designs and typical applications. contact xilinx for design considerations requiring more detailed information. all specifications are subject to change without notice. virtex-ii dc characteristics recommended operating conditions table 30: absolute maximum ratings symbol description units v ccint internal supply voltage relative to gnd -0.5 to 1.65 v v ccaux auxiliary supply voltage relative to gnd -0.5 to 4.0 v v cco output drivers supply voltage relative to gnd -0.5 to 4.0 v v batt key memory battery backup supply -0.5 to 4.0 v v ref input reference voltage -0.5 to 4.0 v v in input voltage relative to gnd (user and dedicated i/os) -0.5 to 4.0 v v ts voltage applied to 3-state output (user and dedicated i/os) -0.5 to 4.0 v v ccint longest supply voltage rise time from 0 v - 1.425 v 50 ms t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temp. +220 c t j operating junction temperature +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. power supplies might turn on in any order. symbol description min max units v ccint internal supply voltage relative to gnd, t j =0 c to +85 c commercial 1.425 1.575 v internal supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.425 1.575 v v ccaux auxiliary supply voltage relative to gnd, t j =0 c to +85 ccommercial3.03.6v auxiliary supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 3.0 3.6 v v cco supply voltage relative to gnd, t j =0 c to +85 ccommercial1.23.6v supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.2 3.6 v v batt battery voltage relative to gnd, t j =0 c to +85 ccommercial1.03.6v battery voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.0 3.6 v notes: 1. if v ccaux and v cco are both at 3.3v, they must use a common supply voltage.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 77 advance product specification 1-800-255-7778 r dc characteristics over recommended operating conditions power-on power supply requirements xilinx fpgas require a certain amount of supply current during power-on to insure proper device operation. the actual current consumed depends on the power-on ramp rate of the power supply. this is the time required to reach the nominal power supply voltage of the device 1 from 0 v. the current is highest at the fastest suggested ramp rate (0 v to nominal voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 v to nominal voltage in 50 ms). symbol description device min max units v drint data retention v ccint voltage (below which configuration data might be lost) all 1.2 v v dri data retention v ccaux voltage (below which configuration data might be lost) all 2.5 v i ccintq quiescent v ccint supply current 1 device dependent i ccoq quiescent v cco supply current 1 device dependent i ccauxq quiescent v ccaux supply current 1 device dependent i ref v ref current per bank all m a i l input or output leakage current all m a c in input capacitance (sample tested) all pf i rpu pad pull-up (when selected) @ v in = 0 v, v cco = 3.3 v (sample tested) all note 2 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) all note 2 ma notes: 1. with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 2. internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. these pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. 3. data are retained even if v cco drops to 0 v. product description 2 current requirement 3 virtex-ii family, commercial grade minimum required current supply 500 ma virtex-ii family, industrial grade minimum required current supply 500 ma notes: 1. ramp rate used for this specification is from 0 to 1.5 v dc. peak current occurs on or near the internal power-on reset thresh old and lasts for less than 3 ms. 2. devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. larger currents may result if ramp rates are forced to be faster.
virtex-ii 1.5v field-programmable gate arrays 78 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ldt dc specifications (ldt_25) input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl (note 1) ? 0.5 0.8 2.0 3.6 0.4 2.4 24 ? 24 lvcmos33 ? 0.5 0.8 2.0 3.6 0.4 v cco ? 0.4 24 ? 24 lvcmos25 ? 0.5 0.7 1.7 2.7 0.4 v cco ? 0.4 24 ? 24 lvcmos18 ? 0.5 20% v cco 70% v cco 1.95 0.4 v cco ? 0.45 16 ? 16 lvcmos15 ? 0.5 20% v cco 70% v cco 1.65 0.4 v cco ? 0.45 16 ? 16 pci33_3 ? 0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco note 2 note 2 pci66_3 ? 0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco note 2 note 2 pci-x ? 0.5 note 2 note 2 note 2 note 2 note 2 note 2 note 2 gtlp ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.6 n/a 36 n/a gtl ? 0.5 v ref ? 0.05 v ref + 0.05 3.6 0.4 n/a 40 n/a hstl i ? 0.5 v ref ? 0.1 v ref + 0.1 1.5 0.4 v cco ? 0.4 8 ? 8 hstl ii ? 0.5 v ref ? 0.1 v ref + 0.1 1.5 0.4 v cco ? 0.4 16 ? 16 hstl iii ? 0.5 v ref ? 0.1 v ref + 0.1 1.5 0.4 v cco ? 0.4 24 ? 8 hstl iv ? 0.5 v ref ? 0.1 v ref + 0.1 1.5 0.4 v cco ? 0.4 48 ? 8 sstl3 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.6 v ref + 0.6 8 ? 8 sstl3 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.8 v ref + 0.8 16 ? 16 sstl2 i ? 0.5 v ref ? 0.2 v ref + 0.2 2.7 v ref ? 0.65 v ref + 0.65 7.6 ? 7.6 sstl2 ii ? 0.5 v ref ? 0.2 v ref + 0.2 2.7 v ref ? 0.80 v ref + 0.80 15.2 ? 15.2 agp-2x ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 10% v cco 90% v cco note 2 note 2 notes: 1. v ol and v oh for lower drive currents are sample tested. 2. tested according to the relevant specifications. dc parameter symbol conditions min typ max units differential output voltage v od r t = 100 ohm across q and q signals 530 600 740 mv change in v od magnitude d v od r t = 100 ohm across q and q signals 30 mv output common mode voltage v os r t = 100 ohm across q and q signals 550 600 680 mv change in v os magnitude d v os 30 mv
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 79 advance product specification 1-800-255-7778 r lvds dc specifications (lvds_33 & lvds_25) extended lvds dc specifications (lvdsext_33 & lvdsext_25) lvpecl dc specifications these values are valid when driving a 100 w differential load only, i.e., a 100 w resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. the following table summarizes the dc output specifications of lvpecl. dc parameter symbol conditions min typ max units supply voltage v cco 3.3 or 2.5 v output high voltage for q and q v oh r t = 100 w across q and q signals 1.475 v output low voltage for q and q v ol r t = 100 w across q and q signals 0.925 v differential output voltage (q ? q ), q = high (q ? q), q = high v odiff r t = 100 w across q and q signals 250 350 400 mv output common-mode voltage v ocm r t = 100 w across q and q signals 1.125 1.2 1.275 v differential input voltage (q ? q ), q = high (q ? q), q = high v idiff common-mode input voltage = 1.25 v 100 350 na mv input common-mode voltage v icm differential input voltage = 350 mv 0.2 1.25 2.2 v dc parameter symbol conditions min typ max units supply voltage v cco 3.3 or 2.5 v output high voltage for q and q v oh r t = 100 w across q and q signals 1.70 v output low voltage for q and q v ol r t = 100 w across q and q signals 0.705 v differential output voltage (q ? q ), q = high (q ? q), q = high v odiff r t = 100 w across q and q signals 440 820 mv output common-mode voltage v ocm r t = 100 w across q and q signals 1.125 1.200 1.275 v differential input voltage (q ? q ), q = high (q ? q), q = high v idiff common-mode input voltage = 1.25 v mv input common-mode voltage v icm differential input voltage = 350 mv v dc parameter min max min max min max units v cco 3.0 3.3 3.6 v v oh 1.8 2.11 1.92 2.28 2.13 2.41 v v ol 0.96 1.27 1.06 1.43 1.30 1.57 v v ih 1.49 2.72 1.49 2.72 1.49 2.72 v v il 0.86 2.125 0.86 2.125 0.86 2.125 v differential input voltage 0.3 - 0.3 - 0.3 - v
virtex-ii 1.5v field-programmable gate arrays 80 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r virtex-ii performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-ii devices. the numbers reported here are worst-case values; they have all been fully characterized. note that these values are subject to the same guidelines as "virtex-ii switching characteristics" on page 81 (speed files). the following table provides pin-to-pin values (in nanosec- onds) including iob delays; that is, delay through the device from input pin to output pin. in the case of multiple inputs and outputs, the worst delay is reported. the following table shows internal (register-to-register) per- formance. values are reported in mhz. description pin to pin (w/ i/o delays) device used & speed grade basic functions 16-bit address decoder 32-bit address decoder 64-bit address decoder 4:1 mux 8:1 mux 16:1 mux 32:1 mux combinatorial (pad to lut to pad) memory block ram pad to setup clock to pad distributed ram pad to setup clock to pad description register to register performance device used & speed grade basic functions 16-bit address decoder 32-bit address decoder 64-bit address decoder 4:1 mux 8:1 mux 16:1 mux 32:1 mux register to lut to register 8-bit adder 16-bit adder 64-bit adder 64-bit counter 64-bit accumulators multiplier 18x18 (with block ram inputs) multiplier 18x18 (with register inputs) memory block ram single-port 4096 x 4 bits single-port 2048 x 9 bits single-port 1024 x 18 bits single-port 512 x 36 bits dual-port a:4096 x 4 bits & b:1024 x 18 bits dual-port a:1024 x 18 bits & b:1024 x 18 bits dual-port a:2048 x 9 bits & b: 512 x 36 bits distributed ram single-port 32 x 8-bit single-port 64 x 8-bit single-port 128 x 8-bit dual-port 16 x 8 dual-port 32 x 8 dual-port 64 x 8 dual-port 128 x 8 shift registers 128-bit srl 256-bit srl fifos (async. in block ram) 1024 x 18-bit 1024 x 18-bit fifos (sync. in srl) 128 x 8-bit 128 x 16-bit cams in block ram 32 x 9-bit 64 x 9-bit 128 x 9-bit 256 x 9-bit cams in srl 32 x 16-bit 64 x 32-bit 128 x 40-bit 256 x 48-bit 1024 x 16-bit 1024 x 72-bit description register to register performance device used & speed grade
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 81 advance product specification 1-800-255-7778 r virtex-ii switching characteristics switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or final. not e that "virtex-ii performance characteristics" on page 80 are subject to these guidelines, as well. the status of each designation is defined as follows: advance : these speed files are based on additional simulation and testing of some family members. although speed grades with this designation are considered relatively stable, some under-reporting might still occur. all family members do not necessarily transition to ? advance ? at the same time. typically, the slowest speed grades transition to ? advance ? before faster speed grades. preliminary : preliminary speed files are based on full device characterization. devices and speed grades with this designation are considered safe for use in production designs. there are no under-reported delays. final : final speed files are released once the family has enough production history and full correlation between the speeds files and devices is established over numerous production lots. all specifications are always representative of worst-case supply voltage and junction temperature conditions. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-ii devices. iob input switching characteristics input delays associated with the pad are specified for lvttl levels. for other standards, adjust the delays with the values shown in "iob input switching characteristics standard adjustments" on page 82 . speed grade description symbol device -6 -5 -4 units propagation delays pad to i output, no delay t iopi all 1.03 1.19 ns, max pad to i output, with delay t iopid 1.33 1.53 ns, max propagation delays pad to output iq via transparent latch, no delay t iopli all 1.28 1.48 ns, max pad to output iq via transparent latch, with delay t ioplid 1.50 1.73 ns, max clock clk to output iq t iockiq all 1.10 1.26 ns, max setup and hold times with respect to clock at iob input register pad, no delay t iopick /t ioickp all 1.11 / 0 1.28 / 0 ns, min pad, with delay t iopickd /t ioickpd 1.41 / 0 1.62 / 0 ns, min ice input t ioiceck /t iockice all 0.20 / 0.04 0.23 / 0.04 ns, min sr input (iff, synchronous) t iosrcki all 0.52 0.60 ns, min set/reset delays sr input to iq (asynchronous) t iosriq all 0.85 0.98 ns, max gsr to output iq t gsrq all 8.25 9.49 ns, max notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. 2. input timing for lvttl is measured at 1.4 v. for other i/o standards, see table 32 .
virtex-ii 1.5v field-programmable gate arrays 82 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r iob input switching characteristics standard adjustments speed grade description symbol standard -6 -5 -4 units data input delay adjustments standard-specific data input delay adjustments t ilvttl lvttl ns t ilvcmos33 lvcmos33 ns t ilvcmos25 lvcmos25 ns t ilvcmos18 lvcmos18 ns t ilvcmos15 lvcmos15 ns t ilvds_25 lvds_25 ns t ilvds_33 lvds_33 ns t ilvpecl_33 lvpecl ns t ipci_33_3 pci, 33 mhz, 3.3 v ns t ipci_66_3 pci, 66 mhz, 3.3 v ns t ipcix pci-x, 133 mhz, 3.3 v ns t igtl gtl ns t igtlplus gtlp ns t ihstl_i hstl i ns t ihstl_ii hstl ii ns t ihstl_iii hstl iii ns t ihstl_iv hstl iv ns t isstl2_i sstl2 i ns t isstl2_ii sstl2 ii ns t isstl3_i sstl3 i ns t isstl3_ii sstl3 ii ns t iagp agp-2x ns t ilvdci33 lvdci_33 ns t ilvdci25 lvdci_25 ns t ilvdci18 lvdci_18 ns t ilvdci15 lvdci_15 ns t ilvdci_dv2_33 lvdci_dv2_33 ns t ilvdci_dv2_25 lvdci_dv2_25 ns t ilvdci_dv2_18 lvdci_dv2_18 ns t ilvdci_dv2_15 lvdci_dv2_15 ns t igtl_dci gtl_dci ns
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 83 advance product specification 1-800-255-7778 r t igtlp_dci gtlp_dci ns t ihstl_i_dci hstl_i_dci ns t ihstl_ii_dci hstl_ii_dci ns t ihstl_iii_dci hstl_iii_dci ns t ihstl_iv_dci hstl_iv_dci ns t isstl2_i_dci sstl2_i_dci ns t isstl2_ii_dci sstl2_ii_dci ns t isstl3_i_dci sstl3_i_dci ns t isstl3_ii_dci sstl3_ii_dci ns t ildt_25 ldt_25 ns t iulvds_25 ulvds_25 ns notes: 1. input timing for lvttl is measured at 1.4 v. for other i/o standards, see table 32 . speed grade description symbol standard -6 -5 -4 units
virtex-ii 1.5v field-programmable gate arrays 84 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r iob output switching characteristics output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays with the values shown in "iob output switching characteristics standard adjustments" on page 85 . speed grade description symbol -6 -5 -4 units propagation delays o input to pad t ioop 4.40 5.06 ns, max o input to pad via transparent latch t ioolp 4.65 5.34 ns, max 3-state delays t input to pad high-impedance (note 2) t iothz 1.53 1.76 ns, max t input to valid data on pad t ioton 4.03 4.64 ns, max t input to pad high-impedance via transparent latch (note 2) t iotlphz 1.78 2.05 ns, max t input to valid data on pad via transparent latch t iotlpon 4.28 4.93 ns, max gts to pad high impedance (note 2) t gts 6.23 7.16 ns, max sequential delays clock clk to pad t iockp 5.05 5.80 ns, max clock clk to pad high-impedance (synchronous) (note 2) t iockhz 2.33 2.68 ns, max clock clk to valid data on pad (synchronous) t iockon 4.83 5.55 ns, max setup and hold times before/after clock clk o input t ioock /t iocko 0.52 / 0 0.60 / 0 ns, min oce input t iooceck /t iockoce 0.20 / 0 0.23 / 0 ns, min sr input (off) t iosrcko /t iockosr 0.52 / 0 0.60 / 0 ns, min 3-state setup times, t input t iotck /t iockt 0.38 / 0 0.44 / 0 ns, min 3-state setup times, tce input t iotceck /t iocktce 0.15 / 0 0.18 / 0 ns, min 3-state setup times, sr input (tff) t iosrckt /t iocktsr 0.52 / 0 0.60 / 0 ns, min set/reset delays sr input to pad (asynchronous) t iosrp 4.80 5.52 ns, max sr input to pad high-impedance (asynchronous) (note 2) t iosrhz 2.08 2.39 ns, max sr input to valid data on pad (asynchronous) t iosron 4.58 5.27 ns, max gsr to pad t iogsrq 5.75 6.61 ns, max notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. 2. the 3-state turn-off delays should not be adjusted.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 85 advance product specification 1-800-255-7778 r iob output switching characteristics standard adjustments output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays by the values shown. speed grade description symbol standard -6 -5 -4 units output delay adjustments standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, csl) t olvttl_s2 lvttl, slow, 2 ma ns t olvttl_s4 4 ma ns t olvttl_s6 6 ma ns t olvttl_s8 8 ma ns t olvttl_s12 12 ma ns t olvttl_s16 16 ma ns t olvttl_s24 24 ma ns t olvttl_f2 lvttl, fast, 2 ma ns t olvttl_f4 4 ma ns t olvttl_f6 6 ma ns t olvttl_f8 8 ma ns t olvttl_f12 12 ma ns t olvttl_f16 16 ma ns t olvttl_f24 24 ma ns t olvds_25 lvds ns t olvds_33 lvds ns t olvdsext_25 lvds ns t olvdsext_33 lvds ns t oldt_25 ldt ns t oblvds_25 blvds ns t oulvds_25 ulvds ns t olvpecl_33 lvpecl ns t opci_33_3 pci, 33 mhz, 3.3 v ns t opci_66_3 pci, 66 mhz, 3.3 v ns t opcix pci-x, 133 mhz, 3.3 v ns t ogtl gtl ns t ogtlp gtlp ns t ohstl_i hstl i ns t ohstl_ii hstl ii ns t ohstl_iiii hstl iii ns t ohstl_iv hstl iv ns t osstl2_i sstl2 i ns t osstl2_ii sstl2 ii ns
virtex-ii 1.5v field-programmable gate arrays 86 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r t osstl3_i sstl3 i ns t osstl3_ii sstl3 ii ns t oagp agp-2x ns t olvcmos33_s2 lvcmos33, slow, 2 ma ns t olvcmos33_s4 4 ma ns t olvcmos33_s6 6 ma ns t olvcmos33_s8 8 ma ns t olvcmos33_s12 12 ma ns t olvcmos33_s16 16 ma ns t olvcmos33_s24 24 ma ns t olvcmos33_f2 lvcmos33, fast, 2 ma ns t olvcmos33_f4 4 ma ns t olvcmos33_f6 6 ma ns t olvcmos33_f8 8 ma ns t olvcmos33_f12 12 ma ns t olvcmos33_f16 16 ma ns t olvcmos33_f24 24 ma ns t olvcmos25_s2 lvcmos25, slow, 2 ma ns t olvcmos25_s4 4 ma ns t olvcmos25_s6 6 ma ns t olvcmos25_s8 8 ma ns t olvcmos25_s12 12 ma ns t olvcmos25_s16 16 ma ns t olvcmos25_s24 24 ma ns t olvcmos25_f2 lvcmos25, fast, 2 ma ns t olvcmos25_f4 4 ma ns t olvcmos25_f6 6 ma ns t olvcmos25_f8 8 ma ns t olvcmos25_f12 12 ma ns t olvcmos25_f16 16 ma ns t olvcmos25_f24 24 ma ns t olvcmos18_s2 lvcmos18, slow, 2 ma ns t olvcmos18_s4 4 ma ns t olvcmos18_s6 6 ma ns t olvcmos18_s8 8 ma ns t olvcmos18_s12 12 ma ns t olvcmos18_s16 16 ma ns speed grade description symbol standard -6 -5 -4 units
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 87 advance product specification 1-800-255-7778 r t olvcmos18_f2 lvcmos18, fast, 2 ma ns t olvcmos18_f4 4 ma ns t olvcmos18_f6 6 ma ns t olvcmos18_f8 8 ma ns t olvcmos18_f12 12 ma ns t olvcmos18_f16 16 ma ns t olvcmos15_s2 lvcmos15, slow, 2 ma ns t olvcmos15_s4 4 ma ns t olvcmos15_s6 6 ma ns t olvcmos15_s8 8 ma ns t olvcmos15_s12 12 ma ns t olvcmos15_s16 16 ma ns t olvcmos15_f2 lvcmos15, fast, 2 ma ns t olvcmos15_f4 4 ma ns t olvcmos15_f6 6 ma ns t olvcmos15_f8 8 ma ns t olvcmos15_f12 12 ma ns t olvcmos15_f16 16 ma ns t olvdci33 lvdci_33 ns t olvdci25 lvdci_25 ns t olvdci18 lvdci_18 ns t olvdci15 lvdci_15 ns t olvdci_dv2_33 lvdci_dv2_33 ns t olvdci_dv2_25 lvdci_dv2_25 ns t olvdci_dv2_18 lvdci_dv2_18 ns t olvdci_dv2_15 lvdci_dv2_15 ns t ogtl_dci gtl_dci ns t ogtlp_dci gtlp_dci ns t ohstl_i_dci hstl_i_dci ns t ohstl_ii_dci hstl_ii_dci ns t ohstl_iii_dci hstl_iii_dci ns t ohstl_iv_dci hstl_iv_dci ns t osstl2_i_dci sstl2_i_dci ns t osstl2_ii_dci sstl2_ii_dci ns t osstl3_i_dci sstl3_i_dci ns t osstl3_ii_dci sstl3_ii_dci ns speed grade description symbol standard -6 -5 -4 units
virtex-ii 1.5v field-programmable gate arrays 88 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r calculation of t ioop as a function of capacitance t ioop is the propagation delay from the o input of the iob to the pad. the values for t ioop are based on the standard capacitive load (c sl ) for each i/o standard, as listed in table 31 . for other capacitive loads, use the formulas below to calcu- late the corresponding t ioop . t ioop = t ioop + t opadjust + (c load ? c sl ) * fl where: t opadjust is reported above in the output delay adjustment section. c load is the capacitive load for the design. table 31: constants for use in calculation of t ioop standard csl (pf) fl (ns/pf) lvttl fast slew rate, 2ma drive 35 lvttl fast slew rate, 4ma drive 35 lvttl fast slew rate, 6ma drive 35 lvttl fast slew rate, 8ma drive 35 lvttl fast slew rate, 12ma drive 35 lvttl fast slew rate, 16ma drive 35 lvttl fast slew rate, 24ma drive 35 lvttl slow slew rate, 2ma drive 35 lvttl slow slew rate, 4ma drive 35 lvttl slow slew rate, 6ma drive 35 lvttl slow slew rate, 8ma drive 35 lvttl slow slew rate, 12ma drive 35 lvttl slow slew rate, 16ma drive 35 lvttl slow slew rate, 24ma drive 35 lvcmos33 35 lvcmos25 35 lvcmos18 35 lvcmos15 35 pci 33mhz 3.3 v 10 pci 66 mhz 3.3 v 10 pci-x 133 mhz 3.3 v 10 gtl 0 gtlp 0 hstl class i 20 hstl class ii 20 hstl class iii 20 hstl class iv 20 sstl2 class i 30 sstl2 class ii 30 sstl3 class i 30 sstl3 class ii 30 agp-2x 10 notes: 1. i/o parameter measurements are made with the capacitance values shown above. 2. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it. table 32: delay measurement methodology standard v l 1 v h 1 meas. point v ref (typ) 2 lvttl 0 3 1.4 - lvcmos33 0 3.3 1.65 - lvcmos25 0 2.5 1.125 - lvcmos18 0 1.8 0.9 - lvcmos15 0 1.5 0.75 - pci33_3 per pci specification - pci66_3 per pci specification - pcix33_3 per pci-x specification - gtl v ref ? 0.2 v ref +0.2 v ref 0.80 gtlp v ref ? 0.2 v ref +0.2 v ref 1.0 hstl class i v ref ? 0.5 v ref +0.5 v ref 0.75 hstl class ii v ref ? 0.5 v ref +0.5 v ref 0.75 hstl class iii v ref ? 0.5 v ref +0.5 v ref 0.90 hstl class iv v ref ? 0.5 v ref +0.5 v ref 0.90 sstl3 i & ii v ref ? 1.0 v ref +1.0 v ref 1.5 sstl2 i & ii v ref ? 0.75 v ref +0.75 v ref 1.25 agp-2x v ref ? (0.2xv cco ) v ref + (0.2xv cco ) v ref per agp spec lvds_25 1.2 lvds_33 1.2 lvdsext_25 1.2 lvdsext_33 1.2
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 89 advance product specification 1-800-255-7778 r clock distribution switching characteristics ulvds_25 0.6 ldt_25 0.6 lvpecl 1.6 ? 0.3 1.6 + 0.3 1.6 notes: 1. input waveform switches between v l and v h . 2. measurements are made at v ref (typ), maximum, and minimum. worst-case values are reported. 3. i/o parameter measurements are made with the capacitance values shown in table 31 . 4. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it. 5. use of ibis models results in a more accurate prediction of the propagation delay: a. model the output in an ibis simulation into the standard capacitive load. b. record the relative time to the v oh or v ol transition of interest. c. remove the capacitance, and model the actual pcb traces (transmission lines) and actual loads from the appropriate ibis models for driven devices. d. record the results from the new simulation. e. compare with the capacitance simulation. the increase or decrease in delay from the capacitive load delay simulation should be added or subtracted from the value above to predict the actual delay. table 32: delay measurement methodology standard v l 1 v h 1 meas. point v ref (typ) 2 description symbol speed grade units -6 -5 -4 gclk iob and buffer global clock pad to output. t gpio 0.34 0.39 ns, max global clock buffer i input to o output t gio 0.50 0.58 ns, max
virtex-ii 1.5v field-programmable gate arrays 90 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r clb switching characteristics delays originating at f/g inputs vary slightly according to the input used (see figure 15 ). the values listed below are worst- case. precise values are provided by the timing analyzer. description symbol speed grade units -6 -5 -4 combinatorial delays 4-input function: f/g inputs to x/y outputs t ilo 0.44 0.50 ns, max 5-input function: f/g inputs to f5 output t if5 0.64 0.73 ns, max 5-input function: f/g inputs to x output t if5x 0.81 0.93 ns, max fxina or fxinb inputs to y output via muxfx t ifxy 0.37 0.43 ns, max fxina input to fx output via muxfx t inafx 0.29 0.33 ns, max fxinb input to fx output via muxfx t inbfx 0.29 0.33 ns, max sopin input to sopout output via orcy t sopsop 0.78 0.90 ns, max incremental delay routing through transparent latch to xq/yq outputs t ifnctl 0.41 0.47 ns, max sequential delays ff clock clk to xq/yq outputs t cko 0.41 0.48 ns, max latch clock clk to xq/yq outputs t cklo 1.10 1.26 ns, max setup and hold times before/after clock clk bx/by inputs t dick /t ckdi 0.31 / 0 0.36 / 0 ns, min dy inputs t dyck /t ckdy 0.24 / 0 0.27 / 0 ns, min dx inputs t dxck /t ckdx 0.24 / 0 0.27 / 0 ns, min ce input t ceck /t ckce 0.20 / 0 0.23 / 0 ns, min sr/by inputs (synchronous) t rck/ t ckr 0.17 / 0.08 0.20 / 0.09 ns, min clock clk minimum pulse width, high t ch 0.54 0.62 ns, min minimum pulse width, low t cl 0.54 0.62 ns, min set/reset minimum pulse width, sr/by inputs t rpw 0.54 0.62 ns, min delay from sr/by inputs to xq/yq outputs (asynchronous) t rq 0.44 0.51 ns, max toggle frequency (mhz) (for export control) f tog 934.58 813.67 mhz notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 91 advance product specification 1-800-255-7778 r clb distributed ram switching characteristics clb shift register switching characteristics description symbol speed grade units -6 -5 -4 sequential delays clock clk to x/y outputs (we active) in 16 x 1 mode t shcko16 1.82 2.09 ns, max clock clk to x/y outputs (we active) in 32 x 1 mode t shcko32 2.09 2.41 ns, max clock clk to f5 output t shckof5 1.92 2.21 ns, max setup and hold times before/after clock clk bx/by data inputs (din) t ds /t dh 0.64 / 0 0.73 / 0 ns, min f/g address inputs t as /t ah 0.42 / 0 0.48 / 0 ns, min ce input (we) t wes /t weh 0.44 / 0 0.51 / 0 ns, min clock clk minimum pulse width, high t wph 2.10 2.42 ns, min minimum pulse width, low t wpl 2.10 2.42 ns, min minimum clock period to meet address write cycle time t wc 4.20 4.83 ns, min notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. description symbol speed grade units -6 -5 -4 sequential delays clock clk to x/y outputs t reg 0.31 0.35 ns, max clock clk to xb output via mc15 lut output t regxb 0.13 0.15 ns, max clock clk to yb output via mc15 lut output t regyb 0.75 0.86 ns, max clock clk to shiftout t cksh 0.12 0.14 ns, max clock clk to f5 output t regf5 0.41 0.47 ns, max setup and hold times before/after clock clk bx/by data inputs (din) t srlds /t srldh 0.31 / 0 0.36 / 0 ns, min ce input (ws) t wss /t wsh 0.20 / 0.04 0.23 / 0.04 ns, min clock clk minimum pulse width, high t srph 2.10 2.42 ns, min minimum pulse width, low t srpl 2.10 2.42 ns, min notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time.
virtex-ii 1.5v field-programmable gate arrays 92 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r multiplier switching characteristics description symbol speed grade units -6 -5 -4 propagation delay to output pin input to pin35 t mult 4.18 4.83 ns, max input to pin34 t mult 4.07 4.70 ns, max input to pin33 t mult 3.96 4.58 ns, max input to pin32 t mult 3.85 4.45 ns, max input to pin31 t mult 3.74 4.32 ns, max input to pin30 t mult 3.63 4.20 ns, max input to pin29 t mult 3.52 4.07 ns, max input to pin28 t mult 3.41 3.94 ns, max input to pin27 t mult 3.30 3.81 ns, max input to pin26 t mult 3.19 3.69 ns, max input to pin25 t mult 3.08 3.56 ns, max input to pin24 t mult 2.97 3.43 ns, max input to pin23 t mult 2.86 3.31 ns, max input to pin22 t mult 2.75 3.18 ns, max input to pin21 t mult 2.64 3.05 ns, max input to pin20 t mult 2.53 2.93 ns, max input to pin19 t mult 2.42 2.80 ns, max input to pin18 t mult 2.31 2.67 ns, max input to pin17 t mult 2.20 2.54 ns, max input to pin16 t mult 2.09 2.42 ns, max input to pin15 t mult 1.98 2.29 ns, max input to pin14 t mult 1.87 2.16 ns, max input to pin13 t mult 1.76 2.04 ns, max input to pin12 t mult 1.65 1.91 ns, max input to pin11 t mult 1.54 1.78 ns, max input to pin10 t mult 1.43 1.66 ns, max input to pin9 t mult 1.32 1.53 ns, max input to pin8 t mult 1.21 1.40 ns, max input to pin7 t mult 1.10 1.27 ns, max input to pin6 t mult 0.99 1.15 ns, max input to pin5 t mult 0.88 1.02 ns, max input to pin4 t mult 0.77 0.89 ns, max input to pin3 t mult 0.66 0.77 ns, max input to pin2 t mult 0.55 0.64 ns, max input to pin1 t mult 0.44 0.51 ns, max input to pin0 t mult 0.33 0.39 ns, max
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 93 advance product specification 1-800-255-7778 r block selectram switching characteristics tbuf switching characteristics jtag test access port switching characteristics description symbol speed grade units -6 -5 -4 sequential delays clock clk to dout output t bcko 2.89 3.33 ns, max setup and hold times before clock clk addr inputs t back /t bcka 0.30 / 0.00 0.35 / 0.00 ns, min din inputs t bdck /t bckd 0.30 / 0.00 0.35 / 0.00 ns, min en input t beck /t bcke 1.60 / 1.30 1.84 / 1.50 ns, min rst input t brck /t bckr 1.38 / 1.08 1.59 / 1.25 ns, min wen input t bwck /t bckw 0.60 / 0.30 0.69 / 0.35 ns, min clock clk minimum pulse width, high t bpwh 1.45 1.67 ns, min minimum pulse width, low t bpwl 1.45 1.67 ns, min notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. description symbol speed grade units -6 -5 -4 combinatorial delays in input to out output t io 0.24 0.28 ns, max tri input to out output high-impedance t off 0.46 0.53 ns, max tri input to valid data on out output t on 0.46 0.53 ns, max description symbol speed grade units -6 -5 -4 tms and tdi setup times before tck t taptk ns, min tms and tdi hold times after tck t tcktap ns, min output delay from clock tck to output tdo t tcktdo ns, max maximum tck clock frequency f tck mhz, max
virtex-ii 1.5v field-programmable gate arrays 94 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r virtex-ii pin-to-pin output parameter guidelines all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock input to output delay for lvttl, 12 ma, fast slew rate, with dcm global clock input to output delay for lvttl, 12 ma, fast slew rate, without dcm description symbol device speed grade units -6 -5 -4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, with dcm. for data output with different standards, adjust the delays with the values shown in "iob output switching characteristics standard adjustments" on page 85 . t ickofdcm ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with 35 pf external capacitive load. for other i/o standards and different loads, see table 31 and table 32 . 3. dcm output jitter is already included in the timing calculation. description symbol device speed grade units -6 -5 -4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, without dcm. for data output with different standards, adjust the delays with the values shown in "iob output switching characteristics standard adjustments" on page 85 . t ickof ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with 35 pf external capacitive load. for other i/o standards and different loads, see table 31 and table 32 . 3. dcm output jitter is already included in the timing calculation.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 95 advance product specification 1-800-255-7778 r virtex-ii pin-to-pin input parameter guidelines all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted global clock set-up and hold for lvttl standard, with dcm global clock set-up and hold for lvttl standard without dcm , description symbol device speed grade units -6 -5 -4 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in "iob input switching characteristics standard adjustments" on page 82 . no delay global clock and iff t psdcm /t phdcm ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. dcm output jitter is already included in the timing calculation. description symbol device speed grade units -6 -5 -4 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in "iob input switching characteristics standard adjustments" on page 82 . full delay global clock and iff t psfd /t phfd ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time.
virtex-ii 1.5v field-programmable gate arrays 96 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r dcm timing parameters testing of switching parameters is modeled after testing methods specified by mil-m-38510/605; all devices are 100% functionally tested. because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. the following guidelines reflect worst-case values across the recommended operating conditions. all output jitter and phase specifications are determined through statistical measurement at the package pins. table 33: operating frequency ranges description symbol constraints speed grade units -6 -5 -4 min max min max min max output clocks (low frequency mode) clk0, clk90, clk180, clk270 clkout_freq_1x_lf mhz clk2x, clk2x180 clkout_freq_2x_lf mhz clkdv clkout_freq_dv_lf mhz clkfx, clkfx180 clkout_freq_fx_lf mhz input clocks (low frequency mode) clkin (using dll outputs 1 ) clkin_freq_dll_lf mhz clkin (using clkfx outputs) clkin_freq_fx_lf mhz psclk psclk_freq_lf mhz output clocks (high frequency mode) clk0, clk180 clkout_freq_1x_hf mhz clkdv clkout_freq_dv_hf mhz clkfx, clkfx180 clkout_freq_fx_hf mhz input clocks (high frequency mode) clkin (using dll outputs 1 ) clkin_freq_dll_hf mhz clkin (using clkfx outputs) clkin_freq_fx_hf mhz psclk psclk_freq_hf mhz notes: 1. ?? dll outputs ? is used here to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv.
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 97 advance product specification 1-800-255-7778 r table 34: input clock tolerances description symbol constraints f clkin speed grade units -6 -5 -4 min max min max min max input clock low/high pulse width psclk psclk_pulse < 1mhz ns clkin 2 clkin_pulse 1 - 10 mhz ns 10 - 25 mhz ns 25 - 50 mhz ns 50 - 100 mhz ns 100 - 150 mhz ns 150 - 200 mhz ns 200 - 250 mhz ns 250 - 300 mhz ns 300 - 350 mhz ns 350 - 400 mhz ns > 400 mhz ns input clock period drift (low frequency mode) clkin (using dll outputs 1 ) clkin_per_drift_dll_lf ns clkin (using clkfx outputs) clkin_per_drift_fx_lf ns input clock period drift (high frequency mode) clkin (using dll outputs 1 ) clkin_per_drift_dll_hf ns clkin (using clkfx outputs) clkin_per_drift_fx_hf ns input clock period jitter (low frequency mode) clkin (using dll outputs 1 ) clkin_per_jitt_dll_lf ps clkin (using clkfx outputs) clkin_per_jitt_fx_lf ps input clock period jitter (high frequency mode) clkin (using dll outputs 1 ) clkin_per_jitt_dll_hf ps clkin (using clkfx outputs) clkin_per_jitt_fx_hf ps feedback clock path delay variation clkfb off-chip feedback clkfb_delay_var_ext ns notes: 1. ?? dll outputs ? is used here to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. specification also applies to psclk.
virtex-ii 1.5v field-programmable gate arrays 98 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r table 35: output clock jitter description symbol constraints speed grade units -6 -5 -4 min max min max min max clock synthesis period jitter clk0 clkout_per_jitt_0 ps clk90 clkout_per_jitt_90 ps clk180 clkout_per_jitt_180 ps clk270 clkout_per_jitt_270 ps clk2x, clk2x180 clkout_per_jitt_2x ps clkdv (integer division) clkout_per_jitt_dv1 ps clkdv (non-integer division) clkout_per_jitt_dv2 ps clkfx, clkfx180 clkout_per_jitt_fx ps table 36: output clock phase alignment description symbol constraints speed grade units -6 -5 -4 min max min max min max phase offset between clkin and clkfb clkin/clkfb clkin_clkfb_phase ps phase offset between any dcm outputs all clk* outputs clkout_phase ps duty cycle precision dll outputs 1 clkout_duty_cycle_dll ps clkfx outputs clkout_duty_cycle_fx ps
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 99 advance product specification 1-800-255-7778 r table 37: miscellaneous timing parameters description symbol constraints f clkin speed grade units -6 -5 -4 min max min max min max time required to achieve lock using dll outputs 1 lock_dll > 60mhz us 50 - 60 mhz us 40 - 50 mhz us 30 - 40 mhz us 24 - 30 mhz us using clkfx outputs lock_fx us additional lock time with fine phase shifting lock_dll_fine_shift us fine phase shifting absolute shifting range fine_shift_range ns delay lines tap delay resolution dcm_tap ps notes: 1. ?? dll outputs ? is used here to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. specification also applies to psclk. table 38: parameter cross-reference libraries guide data sheet dll_clkout_{min|max}_lf clkout_freq_{1x|2x|dv}_lf dfs_clkout_{min|max}_lf clkout_freq_fx_lf dll_clkin_{min|max}_lf clkin_freq_dll_lf dfs_clkin_{min|max}_lf clkin_freq_fx_lf dll_clkout_{min|max}_hf clkout_freq_{1x|dv}_hf dfs_clkout_{min|max}_hf clkout_freq_fx_hf dll_clkin_{min|max}_hf clkin_freq_dll_hf dfs_clkin_{min|max}_hf clkin_freq_fx_hf
virtex-ii 1.5v field-programmable gate arrays 100 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r virtex-ii device/package combinations and maximum i/o wire-bond and flip-chip packages are available. table 39 and table 40 show the maximum possible number of user i/os in wire-bond and flip-chip packages, respectively. table 41 shows the number of available user i/os for all device/package combinations. cs denotes wire-bond chip-scale ball grid array (bga) (0.80 mm pitch). fg denotes wire-bond fine-pitch bga (1.00 mm pitch). ff denotes flip-chip fine-pitch bga (1.00 mm pitch). bg denotes standard bga (1.27 mm pitch). bf denotes flip-chip bga (1.27 mm pitch). the number of i/os per package include all user i/os except the 15 control pins (cclk, done, m0, m1, m2, prog_b, pwrdwn_b, tck, tdi, tdo, tms, hswap_en, dxn, dxp, and rsvd) and vbatt. virtex-ii ordering information virtex-ii ordering information is shown in figure 49 table 39: wire-bond packages information package cs144 fg256 fg456 fg676 bg575 bg728 pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27 size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35 i/os 92 172 324 484 408 516 table 40: flip-chip packages information package ff896 ff1152 ff1517 bf957 pitch (mm) 1.00 1.00 1.00 1.27 size (mm) 31 x 31 35 x 35 40 x 40 40 x 40 i/os 624 824 1,108 684 table 41: virtex-ii device/package combinations and maximum number of available i/os (advance information) package available i/os xc2v 40 xc2v 80 xc2v 250 xc2v 500 xc2v 1000 xc2v 1500 xc2v 2000 xc2v 3000 xc2v 4000 xc2v 6000 xc2v 8000 xc2v 10000 cs144 88 92 92 fg256 88 120 172 172 172 fg456 200 264 324 fg676 392 456 484 ff896 432 528 624 ff1152 720 824 824 824 824 ff1517 912 1,104 1,108 1,108 bg575 328 392 408 bg728 456 516 bf957 624 684 684 684 684 684 note: all devices in a particular package are pin-out (footprint) compatible. in addition, the fg456 and fg676 packages are compatible, as are the ff896 and ff1152 packages. figure 49: virtex-ii ordering information example: xc2v1000-5fg456c device type temperature range c = commercial (tj = 0 c to +85 c) i = industrial (tj = -40 c to +100 c) number of pins package type speed grade (-4, -5, -6) ds031_35_050200
virtex-ii 1.5v field-programmable gate arrays ds031 (v1.1) december 6, 2000 www.xilinx.com 101 advance product specification 1-800-255-7778 r revision history this section records the change history for the data sheet. date version revision 11/07/00 1.0 early access draft. 12/06/00 1.1 initial release.
virtex-ii 1.5v field-programmable gate arrays 102 www.xilinx.com ds031 (v1.1) december 6, 2000 1-800-255-7778 advance product specification r

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